sc68c2550b NXP Semiconductors, sc68c2550b Datasheet
sc68c2550b
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sc68c2550b Summary of contents
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... An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC68C2550B operates 3.3 V and 2.5 V and the industrial temperature range, and is available in a plastic LQFP48 package. 2. Features 2 channel UART with Motorola P interface ...
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... V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs Ordering information Package Name Description LQFP48 plastic low profile quad flat package; 48 leads; body 7 Rev. 02 — 28 April 2005 SC68C2550B 7 1.4 mm © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Version SOT313 ...
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... CONTROL RESET REGISTER SELECT CS IRQ INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC68C2550B 9397 750 14941 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs AND LOGIC LOGIC CLOCK AND BAUD RATE GENERATOR LOGIC XTAL1 Rev. 02 — ...
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... Address used to select Channel A or Channel B. A logic LOW selects Channel A, and a logic HIGH selects Channel B. (See Chip Select (active LOW). This pin enables data transfers between the user CPU and the SC68C2550B for the channel(s) addressed. Individual UART sections (A, B) are addressed by A3. See Table 3 ...
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... Clear to Send (active LOW). These inputs are associated with individual UART channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the SC68C2550B. Status can be tested by reading MSR[4]. This pin has no effect on the UART’s transmit or receive operation. ...
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... TX data is connected to the UART RX input, internally. Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC68C2550B. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input ...
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... FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC68C2550B is capable of operation Mbit/s with a 80 MHz clock. With a crystal or external clock input of 7.3728 MHz, the user can select data rates up to 460 ...
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... Philips Semiconductors 6.2 Internal registers The SC68C2550B provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR) ...
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... TX/RX channel control. The programmable Baud Rate Generator (BRG) is capable of operating with a frequency MHz. To obtain maximum data rate necessary to use full rail swing on the clock input. The SC68C2550B can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins ...
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... FIFO in a block sequence determined by the receive trigger level and the transmit FIFO. In this mode, the SC68C2550B sets the TXRDY (or RXRDY) output pin when characters in the transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger level ...
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... Control Interrupts are also operational. 9397 750 14941 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 4). MCR[3:0] register bits are used for controlling loop-back diagnostic testing. Rev. 02 — 28 April 2005 SC68C2550B © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs TRANSMIT FIFO REGISTERS RECEIVE FIFO REGISTERS CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 02 — 28 April 2005 SC68C2550B TRANSMIT TXA, TXB SHIFT REGISTER MCR[ RECEIVE SHIFT RXA, RXB REGISTER RTSA, RTSB CTSA, CTSB DTRA, DTRB ...
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... FIFO/THR, logic 1 = FIFO/THR empty). The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a Receive Serial Shift Register (RSR). Receive data is removed from the SC68C2550B and receive FIFO by reading the RHR register. The receive section provides a mechanism to ...
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... FIFO drops below the trigger level. logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal default condition) logic 1 = enable the RXRDY (ISR level 2) interrupt Rev. 02 — 28 April 2005 SC68C2550B 1 clocks, the start bit time 2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... ISR register loading the THR with new data characters. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[3:0] enables the SC68C2550B in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status ...
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... FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. Receive operation in mode ‘1’: When the SC68C2550B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached Receive Time-Out has occurred, the RXRDY pin will logic 0. ...
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... Interrupt Status Register (ISR) The SC68C2550B provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced ...
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... LCR[2] stop bit length Word length Stop bit length (bit times LCR[1:0] word length LCR[0] Word length Rev. 02 — 28 April 2005 SC68C2550B Table 14) Table 15). Table 16). © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... OP2 output to LOW state. In Loop-back mode, controls MSR[7]. MCR[2] (OP1). OP1A/OP1B are not available as an external signal in the SC68C2550B. This bit is instead used in the Loop-back mode only. In the Loop-back mode, this bit is used to write the state of the modem RI interface signal. MCR[1] ...
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... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC68C2550B and the CPU. Table 18: Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] 9397 750 14941 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs ...
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... A Modem Status Interrupt will be generated. [1] MSR[2] RI logic change (normal default condition) logic 1 = the RI input to the SC68C2550B has changed from a logic logic 1. A Modem Status Interrupt will be generated. [1] MSR[1] DSR logic DSR change (normal default condition) logic 1 = the DSR input to the SC68C2550B has changed state since the last time it was read ...
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... Philips Semiconductors 7.9 Scratchpad Register (SPR) The SC68C2550B provides a temporary data register to store 8 bits of user information. 7.10 SC68C2550B external reset condition Table 20: Register IER FCR ISR LCR MCR LSR MSR SPR DLL DLM Table 21: Output TXA, TXB OP2A, OP2B RTSA, RTSB DTRA, DTRB IRQ 8 ...
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... OL (data bus 1 0.4 OL (other outputs (data bus (other outputs 800 A 1.85 OH (data bus 400 A 1.85 OH (other outputs MHz - 3.5 - Rev. 02 — 28 April 2005 SC68C2550B Min Max Min 0.3 0.6 0.5 2 0.3 0.8 0.5 - 2 ...
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... RCLK [ [2] [3] - 200 Rev. 02 — 28 April 2005 SC68C2550B = 2 3.3 V and 5 V Unit CC Max Min Max - 100 - 33 100 - 24 100 - RCLK RCLK ...
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... Rev. 02 — 28 April 2005 SC68C2550B valid address valid data 002aab087 valid address t d6 valid data 002aab088 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Figure 6. Figure Rev. 02 — 28 April 2005 SC68C2550B change of state t d8 active active t d9 active active t d8 change of state 002aab089 002aaa112 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... data bits 6 data bits 7 data bits 16 baud rate clock Start bit data bits ( Rev. 02 — 28 April 2005 SC68C2550B next data parity Stop Start bit bit bit d10 active t d11 active 002aab090 ...
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... Start bit data bits ( data bits 6 data bits 7 data bits t d12 t d13 16 baud rate clock Rev. 02 — 28 April 2005 SC68C2550B parity Stop bit bit first byte that reaches the trigger level t d15 active data ready t d16 ...
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... data bits 6 data bits 7 data bits t d18 t d17 trigger lead Rev. 02 — 28 April 2005 SC68C2550B next data parity Stop Start bit bit bit d18 transmitter not ready parity stop bit ...
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... 2.5 scale (1) ( 0.27 0.18 7.1 7.1 9.15 9.15 0.5 0.17 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 02 — 28 April 2005 SC68C2550B detail 0.75 0.95 1 0.2 0.12 0.1 0.45 0.55 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SOT313 ...
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... Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 2 Rev. 02 — 28 April 2005 SC68C2550B 3 350 mm so called so called small/thin packages. © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 02 — 28 April 2005 SC68C2550B Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5] [6] not recommended suitable ...
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... Product data sheet - 1, first bullet: added ‘with Motorola P interface’ Section 18 “Trademarks” on page Product data sheet - Rev. 02 — 28 April 2005 SC68C2550B Doc. number 9397 750 14941 34. 9397 750 14698 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Supersedes SC68C2550B_1 - ...
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... Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 02 — 28 April 2005 SC68C2550B © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Interrupt Status Register (ISR 7.5 Line Control Register (LCR 7.6 Modem Control Register (MCR 7.7 Line Status Register (LSR 7.8 Modem Status Register (MSR 7.9 Scratchpad Register (SPR 7.10 SC68C2550B external reset condition . . . . . . 22 8 Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 24 10.1 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 25 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30 12 Soldering ...