sc68c652b NXP Semiconductors, sc68c652b Datasheet - Page 5

• Manufacturer Part Number: sc68c652b
• Description: Sc68c652b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. With 32-byte Fifos, Irda Encoder/decoder, And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 2:
9397 750 14657
Product data sheet
Symbol
D0 to D7
DSRA, DSRB
DTRA, DTRB
GND
IRQ
R/W
n.c.
OP2A, OP2B
RESET
RIA, RIB
RTSA, RTSB
RXA, RXB
RXRDYA,
RXRDYB
Pin description
Pin
44, 45,
46, 47,
48, 1, 2,
3
39, 20
34, 35
17, 24
30
15
12, 25,
29, 37
32, 9
36
41, 21
33, 22
5, 4
31, 18
Type
I/O
I
O
I
O
I
-
O
I
I
O
I
O
…continued
Description
Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for transferring
information to or from the controlling CPU. D0 is the least significant bit and the first data
bit in a transmit or receive serial data stream.
Data Set Ready (active LOW). These inputs are associated with individual UART
channels A and B. A logic 0 (LOW) on these pins indicates the modem or data set is
powered-on and is ready for data exchange with the UART. These pins have no effect
on the UART’s transmit or receive operation.
Data Terminal Ready (active LOW). These outputs are associated with individual
UART channels A and B. A logic 0 (LOW) on these pins indicates that the SC68C652B
is powered-on and ready. These pins can be controlled via the modem control register.
Writing a logic 1 to MCR[0] will set the DTR output to logic 0 (LOW), enabling the
modem. The output of these pins will be a logic 1 after writing a logic 0 to MCR[0], or
after a reset. These pins have no effect on the UART’s transmit or receive operation.
Signal and power ground
Interrupt Request. Interrupts from UART channels A-B are wire-ORed internally to
function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the
interrupt enable register) whenever a UART channel(s) requires service. Individual
channel interrupt status can be determined by addressing each channel through its
associated internal register, using CS and A3. An external pull-up resistor must be
connected between this pin and V
A logic LOW on this pin will transfer the contents of the data bus (D[0:7]) from an
external CPU to an internal register that is defined by address bits A[0:2]. A logic HIGH
on this pin will load the contents of an internal register defined by address bits A[0:2] on
the SC68C652B data bus (D[0:7]) for access by an external CPU.
not connected
Output 2 (user-defined). This function is associated with individual channels A and B.
The state of these pins is defined by the user through the software settings of MCR[3].
OP2A/OP2B is a logic 0 when MCR[3] is set to a logic 1. OP2A/OP2B is a logic 1 when
MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset.
Reset (active LOW). This pin will reset the internal registers and all the outputs. The
UART transmitter output and the receiver input will be disabled during reset time. See
Section 7.11 “SC68C652B external reset condition”
Ring Indicator (active LOW). These inputs are associated with individual UART
channels A and B. A logic 0 on these pins indicates the modem has received a ringing
signal from the telephone line. A logic 1 transition on these input pins generates an
interrupt.
Request to Send (active LOW). These outputs are associated with individual UART
channels, A and B. A logic 0 on the RTS pin indicates the transmitter has data ready
and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this
pin to a logic 0, indicating data is available. After a reset these pins are set to a logic 1.
These pins have no effect on the UART’s transmit or receive operation.
Receive data input. These inputs are associated with individual serial channel data to
the SC68C652B receive input circuits A and B. The RX signal will be a logic 1 during
reset, idle (no data), or when the transmitter is disabled. During the local loop-back
mode, these RX input pins are disabled and TX data is connected to the UART RX input
internally.
Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW when the trigger level
has been reached or the FIFO has at least one character. It goes HIGH when the RX
FIFO is empty.
Rev. 01 — 25 April 2005
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
CC
.
for initialization details.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC68C652B
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