sc68c652b NXP Semiconductors, sc68c652b Datasheet
sc68c652b
Available stocks
Related parts for sc68c652b
sc68c652b Summary of contents
Page 1
... An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC68C652B operates 3.3 V and 2.5 V and the industrial temperature range, and is available in the plastic LQFP48 package. 2. Features 2 channel UART with Motorola ...
Page 2
... Product data sheet Dual UART with 32-byte FIFOs and IrDA encoder/decoder stop bit generation 2 Description plastic low profile quad flat package; 48 leads; body 7 Rev. 01 — 25 April 2005 SC68C652B Version 7 1.4 mm SOT313-2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
Page 3
... R/W CONTROL RESET REGISTER SELECT CS IRQ INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC68C652B 9397 750 14657 Product data sheet Dual UART with 32-byte FIFOs and IrDA encoder/decoder AND LOGIC LOGIC CLOCK AND BAUD RATE GENERATOR LOGIC XTAL1 Rev. 01 — 25 April 2005 ...
Page 4
... Clear to Send (active LOW). These inputs are associated with individual UART channels A and B. A logic 0 (LOW) on the CTS pins indicates the modem or data set is ready to accept transmit data from the SC68C652B. Status can be tested by reading MSR[4]. These pins have no effect on the UART’s transmit or receive operation. ...
Page 5
... These pins have no effect on the UART’s transmit or receive operation. Receive data input. These inputs are associated with individual serial channel data to the SC68C652B receive input circuits A and B. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, these RX input pins are disabled and TX data is connected to the UART RX input internally ...
Page 6
... Description Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC68C652B. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pins are disabled and TX data is internally connected to the UART RX input. ...
Page 7
... The complete status of each channel of the SC68C652B UART can be read at any time during functional operation by the processor. The SC68C652B can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels ...
Page 8
... Philips Semiconductors 6.2 Internal registers The SC68C652B provides two sets of internal registers (A and B) consisting of 17 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control ...
Page 9
... Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS logic 1. If CTS transitions from a logic logic 1 indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6:7]), and the SC68C652B will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. ...
Page 10
... Hardware/software and time-out interrupts The interrupts are enabled by IER[0:3]. Care must be taken when handling these interrupts. Following a reset, if Interrupt Enable Register (IER) bit the SC68C652B will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to continuing operations. The ISR register provides the current singular highest priority interrupt only ...
Page 11
... TX/RX channel control. The programmable Baud Rate Generator is capable of operating with a frequency MHz. To obtain maximum data rate necessary to use full rail swing on the clock input. The SC68C652B can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins ...
Page 12
... DMA operation The SC68C652B FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output pins ...
Page 13
... REGISTERS REGISTER FLOW CONTROL LOGIC MODEM CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 01 — 25 April 2005 SC68C652B TXA, TXB IR ENCODER RXA, RXB IR DECODER RTSA, RTSB CTSA, CTSB DTRA, DTRB DSRA, DSRB (OP1A, OP1B) RIA, RIB (OP2A, OP2B) CDA, CDB 002aab326 © ...
Page 14
... Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’. 9397 750 14657 Product data sheet Dual UART with 32-byte FIFOs and IrDA encoder/decoder details the assigned bit functions for the SC68C652B internal registers. The [1] Bit 7 Bit 6 ...
Page 15
... FIFO/THR, logic 1 = FIFO/THR empty). The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a Receive Serial Shift Register (RSR). Receive data is removed from the SC68C652B and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts ...
Page 16
... FIFO drops below the trigger level. logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal default condition) logic 1 = enable the RXRDY (ISR level 2) interrupt Rev. 01 — 25 April 2005 SC68C652B …continued © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
Page 17
... Philips Semiconductors 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0:3] enables the SC68C652B in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s) ...
Page 18
... FIFO is completely full. It will be a logic 0 when the trigger level has been reached. Receive operation in mode ‘1’: When the SC68C652B is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached Receive Time-Out has occurred, the RXRDY pin will logic 0. ...
Page 19
... Dual UART with 32-byte FIFOs and IrDA encoder/decoder RCVR trigger levels FCR[6] RX FIFO trigger level (bytes FIFO trigger levels FCR[4] TX FIFO trigger level (bytes Rev. 01 — 25 April 2005 SC68C652B © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
Page 20
... Philips Semiconductors 7.4 Interrupt Status Register (ISR) The SC68C652B provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
Page 21
... LCR[2] stop bit length Word length Stop bit length (bit times LCR[1:0] word length LCR[0] Word length Rev. 01 — 25 April 2005 SC68C652B Table 18). Table 19). © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
Page 22
... OP2 output to LOW state. In loop-back mode, controls MSR[7]. MCR[2] (OP1). OP1A/OP1B are not available as an external signal in the SC68C652B. This bit is instead used in the loop-back mode only. In the loop-back mode, this bit is used to write the state of the modem RI interface signal. MCR[1] ...
Page 23
... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC68C652B and the CPU. Table 21: Bit 9397 750 14657 Product data sheet Dual UART with 32-byte FIFOs and IrDA encoder/decoder Line Status Register bits description ...
Page 24
... A modem Status Interrupt will be generated. [1] MSR[2] RI logic change (normal default condition) logic 1 = the RI input to the SC68C652B has changed from a logic logic 1. A modem Status Interrupt will be generated. [1] MSR[1] DSR logic DSR change (normal default condition) logic 1 = the DSR input to the SC68C652B has changed state since the last time it was read ...
Page 25
... Special character detect logic 0 = Special character detect disabled (normal default condition) logic 1 = Special character detect enabled. The SC68C652B compares each incoming receive character with Xoff2 data match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software fl ...
Page 26
... Philips Semiconductors Table 24: Cont [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 7.11 SC68C652B external reset condition Table 25: Register IER FCR ISR LCR MCR LSR MSR SPR DLL DLM Table 26: Output TXA, TXB ...
Page 27
... Product data sheet Dual UART with 32-byte FIFOs and IrDA encoder/decoder Limiting values Parameter Conditions supply voltage voltage at any pin operating temperature storage temperature total power dissipation per package Rev. 01 — 25 April 2005 SC68C652B Min Max Unit - 7 V GND 0 0 ...
Page 28
... OL (data bus 1 0.4 OL (other outputs (data bus (other outputs 800 A 1.85 OH (data bus 400 A 1.85 OH (other outputs 3.5 - 200 - Rev. 01 — 25 April 2005 SC68C652B Min Max Min 0.3 0.6 0.5 2 0.3 0.8 0.5 - 2 ...
Page 29
... RCLK - - - - - [2] [3] - 200 Rev. 01 — 25 April 2005 SC68C652B V = 3.3 V and Max Min Max - 100 - 33 100 - 24 100 - 24 [ RCLK ...
Page 30
... Rev. 01 — 25 April 2005 SC68C652B valid address valid data 002aab087 valid address t d6 valid data 002aab088 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
Page 31
... Figure 6. Figure Rev. 01 — 25 April 2005 SC68C652B change of state t d8 active active t d9 active active t d8 change of state 002aab089 002aaa112 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
Page 32
... data bits 6 data bits 7 data bits 16 baud rate clock Start bit data bits ( Rev. 01 — 25 April 2005 SC68C652B next data parity Stop Start bit bit bit d10 active t d11 active 002aab090 ...
Page 33
... Start bit data bits ( data bits 6 data bits 7 data bits t d12 t d13 16 baud rate clock Rev. 01 — 25 April 2005 SC68C652B parity Stop bit bit first byte that reaches the trigger level t d15 active data ready t d16 ...
Page 34
... Start bit data bits ( data bits 6 data bits 7 data bits t d18 t d17 trigger lead Rev. 01 — 25 April 2005 SC68C652B next data parity Stop Start bit bit bit d18 transmitter not ready parity Stop bit ...
Page 35
... Product data sheet Dual UART with 32-byte FIFOs and IrDA encoder/decoder UART frame data bits start data bits UART frame Rev. 01 — 25 April 2005 SC68C652B stop bit time bit time 16 002aaa212 clock delay ...
Page 36
... 2.5 scale (1) ( 0.27 0.18 7.1 7.1 9.15 9.15 0.5 0.17 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 01 — 25 April 2005 SC68C652B detail 0.75 0.95 1 0.2 0.12 0.1 0.45 0.55 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SOT313 ...
Page 37
... Product data sheet Dual UART with 32-byte FIFOs and IrDA encoder/decoder 2 called small/thin packages. Rev. 01 — 25 April 2005 SC68C652B 3 350 mm so called © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
Page 38
... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 01 — 25 April 2005 SC68C652B Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5] [6] not recommended suitable ...
Page 39
... Least Significant Bit Most Significant Bit Universal Asynchronous Receiver and Transmitter Data sheet status Change notice Product data sheet - Rev. 01 — 25 April 2005 SC68C652B Doc. number Supersedes 9397 750 14657 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
Page 40
... Trademarks Motorola — registered trademark of Motorola, Inc. Rev. 01 — 25 April 2005 SC68C652B © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
Page 41
... Line Control Register (LCR 7.6 Modem Control Register (MCR 7.7 Line Status Register (LSR 7.8 Modem Status Register (MSR 7.9 Scratchpad Register (SPR 7.10 Enhanced Feature Register (EFR 7.11 SC68C652B external reset condition . . . . . . . 26 8 Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 29 10.1 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 30 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 36 12 Soldering ...