sc68c652b NXP Semiconductors, sc68c652b Datasheet - Page 18

• Manufacturer Part Number: sc68c652b
• Description: Sc68c652b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. With 32-byte Fifos, Irda Encoder/decoder, And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14657
Product data sheet
7.3.2 FIFO mode
Table 11:
Bit
7:6
5:4
3
2
1
0
Symbol
FCR[7:6]
FCR[5:4]
FCR[3]
FCR[2]
FCR[1]
FCR[0]
FIFO Control Register bits description
Description
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO equals
the programmed trigger level. However, the FIFO will continue to be loaded
until it is full. Refer to
TX trigger. Logic 0 or cleared is the default condition; TX trigger level = 16.
These bits are used to set the trigger level for the transmit FIFO interrupt.
The SC68C652B will issue a transmit empty interrupt when the number of
characters in FIFO drops below the selected trigger level. Refer to
DMA mode select
Transmit operation in mode ‘0’: When the SC68C652B is in the 68C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY pin
will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the first
character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC68C652B is in 68C450 mode,
or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at
least one character in the receive FIFO, the RXRDY pin will be a logic 0.
Once active, the RXRDY pin will go to a logic 1 when there are no more
characters in the receiver.
Transmit operation in mode ‘1’: When the SC68C652B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when
the transmit FIFO is completely full. It will be a logic 0 when the trigger level
has been reached.
Receive operation in mode ‘1’: When the SC68C652B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,
or a Receive Time-Out has occurred, the RXRDY pin will go to a logic 0.
Once activated, it will go to a logic 1 after there are no more characters in
the FIFO.
XMIT FIFO reset
RCVR FIFO reset
FIFO enable
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition).
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’
when other FCR bits are written to, or they will not be programmed.
Rev. 01 — 25 April 2005
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Table
12.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC68C652B
Table
18 of 41
13.