sc68c652b NXP Semiconductors, sc68c652b Datasheet - Page 21

• Manufacturer Part Number: sc68c652b
• Description: Sc68c652b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. With 32-byte Fifos, Irda Encoder/decoder, And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14657
Product data sheet
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 16:
Table 17:
Table 18:
Table 19:
Bit
7
6
5:3
2
1:0
LCR[5]
X
X
0
0
1
LCR[2]
0
1
1
LCR[1]
0
0
1
1
Line Control Register bits description
LCR[5:3] parity selection
LCR[2] stop bit length
LCR[1:0] word length
LCR[4]
X
0
1
0
1
Word length
5, 6, 7, 8
5
6, 7, 8
LCR[0]
0
1
0
1
Symbol
LCR[7]
LCR[6]
LCR[5:3]
LCR[2]
LCR[1:0]
LCR[3]
0
1
1
1
1
Word length
5
6
7
8
Rev. 01 — 25 April 2005
Description
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
Set parity; even parity; parity enable. Programs the parity conditions
(see
Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length (see
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Table
Stop bit length (bit times)
1
1
2
1
2
17).
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
Table
Table
19).
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
18).
SC68C652B
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