sc68c652b NXP Semiconductors, sc68c652b Datasheet - Page 13

• Manufacturer Part Number: sc68c652b
• Description: Sc68c652b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. With 32-byte Fifos, Irda Encoder/decoder, And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14657
Product data sheet
Fig 4. Internal loop-back mode diagram
RXRDYA, RXRDYB
TXRDYA, TXRDYB
D0 to D7
A0 to A3
RESET
R/W
IRQ
CS
MCR[2] (OP1). Loop-back test data is entered into the transmit holding register via the
user data bus interface, D0 to D7. The transmit UART serializes the data and passes the
serial data to the receive UART via the internal loop-back connection. The receive UART
converts the serial data back into parallel data that is then made available at the user data
interface D0 to D7. The user optionally compares the received data to the initial
transmitted data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational.
SC68C652B
INTERRUPT
REGISTER
CONTROL
CONTROL
DATA BUS
SELECT
LOGIC
LOGIC
LOGIC
AND
Rev. 01 — 25 April 2005
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
XTAL1
GENERATOR
REGISTERS
REGISTERS
CLOCK AND
BAUD RATE
TRANSMIT
CONTROL
CONTROL
RECEIVE
LOGIC
LOGIC
FLOW
FLOW
FIFO
FIFO
XTAL2
TRANSMIT
REGISTER
REGISTER
RECEIVE
CONTROL
SHIFT
SHIFT
MODEM
LOGIC
ENCODER
DECODER
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
IR
IR
SC68C652B
002aab326
TXA, TXB
RXA, RXB
RTSA, RTSB
CTSA, CTSB
DTRA, DTRB
DSRA, DSRB
(OP1A, OP1B)
RIA, RIB
(OP2A, OP2B)
CDA, CDB
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