sc68c652b NXP Semiconductors, sc68c652b Datasheet - Page 22

• Manufacturer Part Number: sc68c652b
• Description: Sc68c652b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. With 32-byte Fifos, Irda Encoder/decoder, And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14657
Product data sheet
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 20:
Bit
7
6
5
4
3
2
1
0
Symbol
MCR[7]
MCR[6]
MCR[5]
MCR[4]
MCR[3]
MCR[2]
MCR[1]
MCR[0]
Modem Control Register bits description
Description
Clock select
IR enable (see
reserved; set to ‘0’
Loop-back. Enable the local loop-back mode (diagnostics). In this mode
the transmitter output (TX) and the receiver input (RX), CTS, DSR, CD,
and RI are disconnected from the SC68C652B I/O pins. Internally the
modem data and control pins are connected into a loop-back data
configuration (see
interrupts remain fully operational. The Modem Control Interrupts are also
operational, but the interrupts’ sources are switched to the lower four bits of
the Modem Control. Interrupts continue to be controlled by the IER
register.
OP2 control
(OP1). OP1A/OP1B are not available as an external signal in the
SC68C652B. This bit is instead used in the loop-back mode only. In the
loop-back mode, this bit is used to write the state of the modem RI
interface signal.
RTS
DTR
Rev. 01 — 25 April 2005
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
logic 0 = enable the standard modem receive and transmit input/output
interface (normal default condition)
logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While
in this mode, the TX/RX output/inputs are routed to the infrared
encoder/decoder. The data input and output levels will conform to the
IrDA infrared interface requirement. As such, while in this mode, the
infrared TX output will be a logic 0 during idle data conditions.
logic 0 = disable loop-back mode (normal default condition)
logic 1 = enable local loop-back mode (diagnostics)
logic 0 = forces OP2 output to HIGH state
logic 1 = forces OP2 output to LOW state. In loop-back mode, controls
MSR[7].
logic 0 = force RTS output to a logic 1 (normal default condition)
logic 1 = force RTS output to a logic 0
logic 0 = force DTR output to a logic 1 (normal default condition)
logic 1 = force DTR output to a logic 0
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Figure
Figure
16)
4). In this mode, the receiver and transmitter
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC68C652B
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