mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 489

• Manufacturer Part Number: mc9s12ne64
• Description: Hcs12 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

18.3.2.12 Debug Comparator B Register (DBGCB)
18.4
This section provides a complete functional description of the DBG module. The DBG module can be
configured to run in either of two modes, BKP or DBG. BKP mode is enabled by setting BKABEN in
DBGC2. DBG mode is enabled by setting DBGEN in DBGC1. Setting BKABEN in DBGC2 overrides the
DBGEN in DBGC1 and prevents DBG mode. If the part is in secure mode, DBG mode cannot be enabled.
18.4.1
In BKP mode, the DBG will be fully backwards compatible with the existing BKP_ST12_A module. The
DBGC2 register has four additional bits that were not available on existing BKP_ST12_A modules. As
long as these bits are written to either all 1s or all 0s, they should be transparent to the user. All 1s would
enable comparator C to be used as a breakpoint, but tagging would be enabled. The match address register
would be all 0s if not modified by the user. Therefore, code executing at address 0x0000 would have to
occur before a breakpoint based on comparator C would happen.
The DBG module in BKP mode supports two modes of operation: dual address mode and full breakpoint
mode. Within each of these modes, forced or tagged breakpoint types can be used. Forced breakpoints
occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just
before the tagged instruction executes. The action taken upon a successful match can be to either place the
CPU in background debug mode or to initiate a software interrupt.
Freescale Semiconductor
Reset
Reset
Field
15:0
15:0
W
W
R
R
Functional Description
Bit 15
DBG Operating in BKP Mode
Bit 7
Comparator B Compare Bits — The comparator B compare bits control whether comparator B compares the
address bus bits [15:0] or data bus bits [15:0] to a logic 1 or logic 0. See
0 Compare corresponding address bit to a logic 0, compares to data if in Full mode
1 Compare corresponding address bit to a logic 1, compares to data if in Full mode
15
0
0
7
Figure 18-20. Debug Comparator B Register High (DBGCBH)
Figure 18-21. Debug Comparator B Register Low (DBGCBL)
Bit 14
Bit 6
14
0
0
6
Table 18-23. DBGCB Field Descriptions
Bit 13
Bit 5
MC9S12NE64 Data Sheet, Rev. 1.1
13
0
0
5
Bit 12
Bit 4
12
0
0
4
Description
Bit 11
Bit 3
11
0
0
3
Bit 10
Table
Bit 2
10
0
0
2
18-20.
Bit 9
Bit 1
0
0
9
1
Functional Description
Bit 8
Bit 0
0
0
8
0
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