mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 256

• Manufacturer Part Number: mc9s12ne64
• Description: Hcs12 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 8 Serial Communication Interface (SCIV3)
8.4.5.5.2
Figure 8-23
instead of RT16 but continues to be sampled at RT8, RT9, and RT10.
For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr
cycles to finish data sampling of the stop bit.
With the misaligned character shown in
the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is:
For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr
cycles to finish data sampling of the stop bit.
With the misaligned character shown in
the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is:
8.4.5.6
To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2
(SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will
continue to load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag.
The transmitting device can address messages to selected receivers by including addressing information
in the initial frame or frames of each message.
The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby
state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark
wakeup.
256
((160 – 154) / 160) x 100 = 3.75%
((176 – 170) / 176) x 100 = 3.40%
shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10
Receiver Wakeup
Fast Data Tolerance
RECEIVER
RT CLOCK
MC9S12NE64 Data Sheet, Rev. 1.1
Figure
Figure
Figure 8-23. Fast Data
STOP
8-23, the receiver counts 154 RTr cycles at the point when
8-23, the receiver counts 170 RTr cycles at the point when
SAMPLES
DATA
IDLE OR NEXT FRAME
Freescale Semiconductor