p89cv51rb2 NXP Semiconductors, p89cv51rb2 Datasheet - Page 44

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p89cv51rb2

Manufacturer Part Number
p89cv51rb2
Description
P89cv51rb2/rc2/rd2 8-bit 80c51 5 V Low Power 64 Kb Flash Microcontroller With 1 Kb Ram, Spi, 6-clock Cpu With 6/12-clock Peripherals
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
P89CV51RB2_RC2_RD2_1
Product data sheet
Table 33.
Table 34.
Table 35.
Bit addressable; reset value: 00H.
Table 36.
Bit
7
6
5 to 3
2 to 1
0
CPS1
0
0
1
1
Bit
7
6
5
4
3
2
1
0
Bit
Symbol
CMOD - PCA counter mode register (address C1H) bit description
CMOD - PCA counter mode register (address C1H) count pulse select
CCON - PCA counter control register (address D8H) bit allocation
CCON - PCA counter control register (address D8H) bit description
Symbol
CIDL
WDTE
-
CPS1,
CPS0
ECF
Symbol
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
CF
7
CPS0
0
1
0
1
Rev. 01 — 5 October 2007
CR
6
Description
Counter Idle control. CIDL = 0 programs the PCA counter to continue
functioning during Idle mode; CIDL = 1 programs it to be gated off
during Idle mode.
WatchDog Timer Enable. WDTE = 0 disables watchdog timer function
on module 4; WDTE = 1 enables it.
Reserved for future use. Should be set to 0 by user programs.
PCA Count Pulse Select; see
PCA Enable Counter overflow interrupt Flag. ECF = 1 enables CF bit
in CCON to generate an interrupt; ECF = 0 disables that function.
Description
PCA Counter overflow Flag. Set by hardware when the counter rolls
over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by
either hardware or software but can only be cleared by software.
PCA Counter Run control. Set by software to turn the PCA counter on.
Must be cleared by software to turn the PCA counter off.
Reserved for future use. Should be set to 0 by user programs.
PCA Module 4 interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
PCA Module 3 interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
PCA Module 2 interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
PCA Module 1 interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
PCA Module 0 interrupt Flag. Set by hardware when a match or
capture occurs. Must be cleared by software.
5
-
Select PCA input
0 internal clock, f
1 internal clock, f
2 Timer 0 overflow
3 external clock at pin P1[2]/ECI (maximum rate = f
P89CV51RB2/RC2/RD2
CCF4
4
osc
osc
CCF3
Table
/ 6
/ 6
3
34.
80C51 with 1 kB RAM, SPI
CCF2
2
© NXP B.V. 2007. All rights reserved.
CCF1
1
osc
CCF0
44 of 73
0
/ 4)

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