p89cv51rb2 NXP Semiconductors, p89cv51rb2 Datasheet - Page 28

• Manufacturer Part Number: p89cv51rb2
• Description: P89cv51rb2/rc2/rd2 8-bit 80c51 5 V Low Power 64 Kb Flash Microcontroller With 1 Kb Ram, Spi, 6-clock Cpu With 6/12-clock Peripherals
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89CV51RB2_RC2_RD2_1
Product data sheet
6.5 Timer 2
Timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event
counter, as selected by C/T2 in the special function register T2CON. Timer 2 has four
operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud rate
generator which are selected according to
and T2MOD
Table 18.
Table 19.
Bit addressable; reset value: 00H.
Table 20.
RCLK + TCLK
0
0
0
1
X
Bit
7
6
5
Bit
Symbol
Fig 10. Timer/counter 0 Mode 3 (two 8-bit counters)
INT0 pin
TnGate
T0 pin
osc/6
TR0
Symbol
TF2
EXF2
RCLK
Timer 2 operating mode
T2CON - Timer/Counter 2 control register (address C8H) bit allocation
T2CON - Timer/Counter 2 control register (address C8H) bit description
(Table 21
TF2
7
CP/RL2
0
1
0
X
X
Description
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by
software. TF2 will not be set when either RCLK or TCLK = 1 or when Timer
2 is in Clock-out mode.
Timer 2 external flag is set when Timer 2 is in capture, reload or baud rate
mode, EXEN2 = 1 and a negative transition on T2EX occurs. If Timer 2
interrupt is enabled EXF2 = 1 causes the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software.
Receive clock flag. When set, causes the UART to use Timer 2 overflow
pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1
overflow to be used for the receive clock.
Rev. 01 — 5 October 2007
and
EXF2
6
osc/2
TR1
C/T = 0
C/T = 1
Table
RCLK
22).
TR2
1
1
1
1
0
5
P89CV51RB2/RC2/RD2
Table 18
TCLK
control
control
4
T2OE
0
0
1
0
X
using T2CON
EXEN2
(8-bits)
(8-bits)
TH0
TL0
3
overflow
overflow
80C51 with 1 kB RAM, SPI
Mode
16-bit auto reload
16-bit capture
Programmable clock-out
Baud rate generator
off
TR2
2
(Table 19
TF0
TF1
© NXP B.V. 2007. All rights reserved.
C/T2
1
and
002aaa522
interrupt
interrupt
Table
CP/RL2
28 of 73
0
20)