p89cv51rb2 NXP Semiconductors, p89cv51rb2 Datasheet - Page 41

• Manufacturer Part Number: p89cv51rb2
• Description: P89cv51rb2/rc2/rd2 8-bit 80c51 5 V Low Power 64 Kb Flash Microcontroller With 1 Kb Ram, Spi, 6-clock Cpu With 6/12-clock Peripherals
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89CV51RB2_RC2_RD2_1
Product data sheet
6.8 Watchdog timer
6.9 PCA
The WDT is intended as a recovery method in situations where the CPU may be
subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog
Timer Reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, the user
must write 01EH and 0E1H, in sequence, to the WDTRST SFR. When the WDT is
enabled, it will increment every machine cycle while the oscillator is running. There is no
way to disable the WDT, except through a reset (either a hardware reset or a WDT
overflow reset). When the WDT overflows, it will drive an output reset HIGH pulse at the
RST pin.
When the WDT is enabled (and thus running) the user needs to reset it by writing 01EH
and 0E1H, in sequence, to the WDTRST SFR to avoid WDT overflow. The 14-bit counter
reaches overflow when it reaches 16383 (3FFFH) and this will reset the device.
The WDT’s counter cannot be read or written. When the WDT overflows it will generate an
output pulse at the RST pin with a duration of 98 oscillator periods in 6-clock mode or 196
oscillator periods in 12-clock mode.
The PCA includes a special 16-bit timer that has five 16-bit capture/compare modules
associated with it. Each of the modules can be programmed to operate in one of four
modes: rising and/or falling edge capture, software timer, high-speed output, or
pulse-width modulator. Each module has a pin associated with it: Module 0 is connected
Fig 17. SPI transfer format with CPHA = 0
Fig 18. SPI transfer format with CPHA = 1
SCK (CPOL = 0)
SCK (CPOL = 1)
SCK (CPOL = 0)
SCK (CPOL = 1)
(for reference)
(for reference)
(from master)
(from master)
SS (to slave)
SS (to slave)
SCK cycle #
SCK cycle #
(from slave)
(from slave)
MOSI
MISO
MOSI
MISO
Rev. 01 — 5 October 2007
MSB
MSB
MSB
MSB
1
1
2
2
6
6
6
6
3
3
5
5
P89CV51RB2/RC2/RD2
5
5
4
4
4
4
4
4
5
5
3
3
3
3
6
6
2
2
2
2
80C51 with 1 kB RAM, SPI
7
7
1
1
1
1
LSB
8
LSB
LSB
8
© NXP B.V. 2007. All rights reserved.
LSB
002aaa529
002aaa530
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