p89cv51rb2 NXP Semiconductors, p89cv51rb2 Datasheet - Page 39

• Manufacturer Part Number: p89cv51rb2
• Description: P89cv51rb2/rc2/rd2 8-bit 80c51 5 V Low Power 64 Kb Flash Microcontroller With 1 Kb Ram, Spi, 6-clock Cpu With 6/12-clock Peripherals
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89CV51RB2_RC2_RD2_1
Product data sheet
Fig 16. SPI master-slave interconnection
CLOCK GENERATOR
6.7.1 SPI features
6.7.2 SPI description
6.7 Serial Peripheral Interface (SPI)
SPI
The serial peripheral interface allows high-speed synchronous data transfer between the
P89CV51RB2/RC2/RD2 and peripheral devices or between several
P89CV51RB2/RC2/RD2 devices.
and slave SPI devices. The SPICLK pin is the clock output and input for the Master and
Slave modes, respectively. The SPI clock generator will start following a write to the
master devices SPI data register. The written data is then shifted out of the MOSI pin of
the master device into the MOSI pin of the slave device. Following a complete
transmission of one byte of data, the SPI clock generator is stopped and the SPI interrupt
Flag (SPIF) is set. An SPI interrupt request will be generated if the SPI Interrupt Enable bit
(SPIE) and the SPI interrupt enable bit, ES, are both set.
An external master drives the Slave Select input pin (SS) LOW to select the SPI module
as a slave. If SS has not been driven LOW, then the slave SPI unit is not active and the
MOSI pin can also be used as an input port pin.
CPHA and CPOL control the phase and polarity of the SPI clock (SCK).
Figure 18
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Master or slave operation
10 MHz bit frequency (max)
LSB first or MSB first data transfer
Four programmable bit rates
End of transmission (SPIF)
Write-collision flag protection (WCOL)
Wake-up from Idle mode (Slave mode only)
8-BIT SHIFT REGISTER
MSB master LSB
show the four possible combinations of these two bits.
Rev. 01 — 5 October 2007
SCK
MISO
MOSI
SS
V
Figure 16
DD
V
MISO
MOSI
P89CV51RB2/RC2/RD2
SS
SCK
SS
shows the correspondence between master
8-BIT SHIFT REGISTER
MSB slave LSB
80C51 with 1 kB RAM, SPI
© NXP B.V. 2007. All rights reserved.
Figure 17
002aaa528
and
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