p89cv51rb2 NXP Semiconductors, p89cv51rb2 Datasheet - Page 26

• Manufacturer Part Number: p89cv51rb2
• Description: P89cv51rb2/rc2/rd2 8-bit 80c51 5 V Low Power 64 Kb Flash Microcontroller With 1 Kb Ram, Spi, 6-clock Cpu With 6/12-clock Peripherals
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89CV51RB2_RC2_RD2_1
Product data sheet
6.4.1 Mode 0
Table 17.
Putting either timer into Mode 0 makes it look like an 8048 timer, which is an 8-bit counter
with a fixed divide-by-32 prescaler.
In this mode, the timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the timer interrupt flag TFn. The count input is enabled to the
timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the timer
to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a
control bit in the special function register TCON
register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper
3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not
clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1; see
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Bit
7
6
5
4
3
2
1
0
Fig 7. Timer/counter 0 or 1 in Mode 0 (13-bit counter)
INTn pin
TnGate
Tn pin
osc/6
TRn
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TCON - Timer/Counter control register (address 88H) bit description
Description
Timer 1 overflow Flag. Set by hardware on timer/counter overflow. Cleared
by hardware when the processor vectors to Timer 1 interrupt routine, or by
software.
Timer 1 Run control bit. Set/cleared by software to turn timer/counter 1
on/off.
Timer 0 overflow Flag. Set by hardware on timer/counter overflow. Cleared
by hardware when the processor vectors to Timer 0 interrupt routine, or by
software.
Timer 0 Run control bit. Set/cleared by software to turn timer/counter 0
on/off.
Interrupt 1 Edge flag. Set by hardware when external interrupt 1
edge/LOW-state is detected. Cleared by hardware when the interrupt is
processed, or by software.
Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/LOW-state that triggers external interrupt 1.
Interrupt 0 Edge flag. Set by hardware when external interrupt 0
edge/LOW-state is detected. Cleared by hardware when the interrupt is
processed, or by software.
Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/LOW-state that triggers external interrupt 0.
Rev. 01 — 5 October 2007
C/T = 0
C/T = 1
Figure 7
P89CV51RB2/RC2/RD2
control
shows Mode 0 operation.
(Table
(5-bits)
TLn
17). The GATE bit is in the TMOD
(8-bits)
THn
Figure
80C51 with 1 kB RAM, SPI
overflow
7. There are two
© NXP B.V. 2007. All rights reserved.
TFn
002aaa519
interrupt
26 of 73