p89cv51rb2 NXP Semiconductors, p89cv51rb2 Datasheet - Page 40

• Manufacturer Part Number: p89cv51rb2
• Description: P89cv51rb2/rc2/rd2 8-bit 80c51 5 V Low Power 64 Kb Flash Microcontroller With 1 Kb Ram, Spi, 6-clock Cpu With 6/12-clock Peripherals
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89CV51RB2_RC2_RD2_1
Product data sheet
Table 27.
Reset source(s): any reset; reset value: 0000 0000B.
Table 28.
Table 29.
Table 30.
Reset source(s): any reset; reset value: 0000 0000B.
Table 31.
Bit
7
6
5
4
3
2
1
0
SPR1
0
0
1
1
Bit
7
6
5 to 0
Bit
Symbol
Bit
Symbol
Symbol
SPIE
SPEN
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
SPCR - SPI control register (address D5H) bit allocation
SPCR - SPI control register (address D5H) bit description
SPCR - SPI control register (address D5H) clock rate selection
SPSR - SPI Status Register (address AAH) bit allocation
SPSR - SPI Status Register (address AAH) bit description
Symbol
SPIF
WCOL
-
SPIE
SPIF
7
7
Description
SPI interrupt enable. If both SPIE = 1 and ES = 1, SPI interrupts are enabled.
SPI enable bit. When set enables SPI.
Data transmission order. 0 = MSB first; 1 = LSB first in data transmission.
Master/Slave select. 1 = Master mode, 0 = Slave mode.
Clock polarity. 1 = SPICLK is HIGH when idle (active LOW), 0 = SPICLK is
LOW when idle (active HIGH).
Clock Phase control bit. 1 = shift-triggered on the trailing edge of the clock;
0 = shift-triggered on the leading edge of the clock.
SPI clock Rate select bit 1. Along with SPR0 controls the SPICLK rate of the
device when a master. SPR1 and SPR0 have no effect on the slave; see
Table
SPI clock Rate select bit 0. Along with SPR1 controls the SPICLK rate of the
device when a master. SPR1 and SPR0 have no effect on the slave; see
Table
SPR0
0
1
0
1
WCOL
Rev. 01 — 5 October 2007
SPEN
29.
29.
6
6
Description
SPI interrupt flag. Upon completion of data transfer, this bit is set to 1.
If SPIE = 1 and ES = 1, an interrupt is then generated. This bit is
cleared by software.
Write Collision flag. Set if the SPI data register is written to during data
transfer. This bit is cleared by software.
Reserved for future use. Should be set to 0 by user programs.
DORD
5
5
-
SPICLK = f
6-clock mode
2
8
32
64
P89CV51RB2/RC2/RD2
MSTR
4
4
-
osc
divided by
CPOL
3
3
-
80C51 with 1 kB RAM, SPI
CPHA
12-clock mode
4
16
64
128
2
2
-
© NXP B.V. 2007. All rights reserved.
SPR1
1
1
-
SPR0
40 of 73
0
0
-