p89cv51rb2 NXP Semiconductors, p89cv51rb2 Datasheet - Page 17

• Manufacturer Part Number: p89cv51rb2
• Description: P89cv51rb2/rc2/rd2 8-bit 80c51 5 V Low Power 64 Kb Flash Microcontroller With 1 Kb Ram, Spi, 6-clock Cpu With 6/12-clock Peripherals
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 10.
P89CV51RB2_RC2_RD2_1
Product data sheet
Device
P89CV51RB2/RC2/RD2
Default boot vector values and ISP entry points
6.3.3 Boot block
6.3.4 Power-on reset code execution
6.3.5 Hardware activation of the bootloader
6.3.6 ISP
6.3.7 Using ISP
When the microcontroller programs its own flash memory, all of the low-level details are
handled by code (bootloader) that is contained in a boot block. A user program calls the
common entry point in the boot block with appropriate parameters to accomplish the
desired operation. Boot block operations include erase user code, program user code,
program security bits, chip erase, etc. The boot block logically overlays the program
memory space from FC00H to FFFFH, when it is enabled. The boot block may be
disabled on-the-fly so that the upper 1 kB of user code is available to the user’s program.
The P89CV51RB2/RC2/RD2 contains two special flash elements: the boot vector and the
boot status bit. Following reset, the P89CV51RB2/RC2/RD2 examines the contents of the
boot status bit. If the boot status bit is set to zero, power-up execution starts at location
0000H, which is the normal start address of the user’s application code. When the boot
status bit is set to a value other than zero, the contents of the boot vector are used as the
high byte of the execution address and the low byte is set to 00H.
Table 10
bootloader is pre-programmed into the address space indicated and uses the indicated
bootloader entry point to perform ISP functions.
The bootloader can also be executed by forcing the device into ISP mode during a
power-on sequence. This has the same effect as having a non-zero status byte. This
allows an application to be built that will normally execute user code but can be manually
forced into ISP operation. This occurs by holding PSEN LOW at the falling edge of reset. If
the factory default setting for the boot vector (FCH) is changed, it will no longer point to the
factory pre-programmed ISP bootloader code. After programming the flash, the status
byte should be programmed to zero in order to allow execution of the user’s application
code beginning at address 0000H.
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89CV51RB2/RC2/RD2 through the serial port. This
firmware is provided by NXP and embedded within each P89CV51RB2/RC2/RD2 device.
The NXP ISP facility has made in-circuit programming in an embedded application
possible with a minimum of additional expense in components and circuit board area. The
ISP function uses five pins (V
needs to be available to interface your application to an external circuit in order to use this
feature.
The ISP feature allows for a wide range of baud rates to be used in your application,
independent of the oscillator frequency. It is also adaptable to a wide range of oscillator
frequencies. This is accomplished by measuring the bit-time of a single bit in a received
Default boot vector
FCH
shows the factory default boot vector setting for this device. A factory-provided
Rev. 01 — 5 October 2007
Default bootloader entry point
FC00H
DD
, V
SS
, TXD, RXD, and RST). Only a small connector
P89CV51RB2/RC2/RD2
Default bootloader code range
FC00H to FFFFH
80C51 with 1 kB RAM, SPI
© NXP B.V. 2007. All rights reserved.
17 of 73