p89cv51rb2 NXP Semiconductors, p89cv51rb2 Datasheet - Page 16

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p89cv51rb2

Manufacturer Part Number
p89cv51rb2
Description
P89cv51rb2/rc2/rd2 8-bit 80c51 5 V Low Power 64 Kb Flash Microcontroller With 1 Kb Ram, Spi, 6-clock Cpu With 6/12-clock Peripherals
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
P89CV51RB2_RC2_RD2_1
Product data sheet
6.3.1 Flash organization
6.3.2 Features
6.3 Flash memory
The P89CV51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block for user
code. The flash can be read or written in bytes and can be erased in 128-B pages. A chip
erase function will erase the entire user code memory and its associated security bits.
There are three methods for erasing or programming the flash memory that may be used.
First, the flash may be programmed or erased in the end-user application by calling
LOW-state routines through a common IAP entry point. Second, the on-chip ISP
bootloader may be invoked. This ISP bootloader will, in turn, call LOW-state routines
through the same common entry point that can be used by the end-user application.
Third, the flash may be programmed or erased using the parallel method by using a
commercially available EPROM programmer which supports this device.
Fig 6. Power-on reset circuit
Flash internal program memory with 128-B page erase.
Internal boot block, containing LOW-state IAP routines available to user code.
Boot vector allows user-provided flash loader code to reside anywhere in the flash
memory space, providing flexibility to the user.
Default loader providing ISP via the serial port, located in upper-end of program
memory.
Programming and erase over the full operating voltage range.
Read/Programming/Erase using ISP/IAP.
Programming with industry-standard commercial programmers.
10000 typical erase/program cycles for each byte.
100 year minimum data retention.
V
Rev. 01 — 5 October 2007
DD
10 F
8.2 k
C 2
C 1
P89CV51RB2/RC2/RD2
RST
XTAL2
XTAL1
V
002aaa543
DD
80C51 with 1 kB RAM, SPI
© NXP B.V. 2007. All rights reserved.
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