at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 759

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

44.2.4
44.2.4.1
44.2.4.2
44.2.4.3
44.2.4.4
44.2.4.5
44.2.5
44.2.5.1
6221G–ATARM–31-Jan-08
MCI
Oscillators
Busy signal of R1b responses is not taken in account
SDIO interrupt does not work for slots different from A
Data Timeout Error Flag
Data Write Operation and number of bytes
Flag Reset is not correct in half duplex mode
On-chip RC startup time
The busy status of the card during the response (R1b) is ignored for the commands CMD7,
CMD28, CMD29, CMD38, CMD42, CMD56. Additionally, for commands CMD42 and CMD56 a
conflict can occur on data line0 if the MCI sends data to the card while the card is still busy.The
behavior is correct for CMD12 command (STOP_TRANSFER).
None
If the data bus width is 1 bit and slots other than slot A chosen, the SDIO interrupt can not be
captured. The sample is made on the bad data line.
None
As the data Timeout error flag checking the Naac timing cannot rise, the MCI can be stalled wait-
ing indefinitely the Data start bit.
A STOP command must be sent with a software timeout.
The Data Write operation with a number of bytes less than 12 is impossible.
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The
BLKLEN or BCNT field are used to specify the real count number.
In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be
incorrect.
These flags are reset correctly after a PDC channel enable.
Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the
PDC channel by writing PDC_TXTEN or PDC_RXTEN.
When booting from the on-chip RC, the startup time is fixed at 1200 ms and not 240 µs as spec-
ified in
None
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Table 6-1 on page
16.
AT91SAM9260
759