at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 396

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at91sam9260-cj

Manufacturer Part Number
at91sam9260-cj
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet

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Figure 31-16. TWI Write Operation with Multiple Data Bytes with or without Internal Address
396
AT91SAM9260
TWI_THR = data to send
Yes
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
- Internal address size
Set the Master Mode register:
TWI_CR = MSEN + SVDIS
Internal address size = 0?
Write ==> bit MREAD = 0
TWI_THR = Data to send
Set the Control register:
- Device slave address
Load Transmit register
- Transfer direction bit
Read Status register
Read Status register
(Needed only once)
- Master enable
TXCOMP = 1?
Yes
Data to send?
Yes
Set TWI clock
TXRDY = 1?
Yes
BEGIN
END
(if IADR used)
No
No
No
Set the internal address
TWI_IADR = address
6221G–ATARM–31-Jan-08

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