at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 758

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

44.2.2
44.2.2.1
44.2.2.2
44.2.3
44.2.3.1
6221G–ATARM–31-Jan-08
Boot ROM
EMAC
NAND Flash Boot does not work correctly
Problem with RTT
TX underrun may occur in some cases
The SMC_SETUP register for the NAND Flash Chip Select (NCS3) is not initialized correctly in
the ROM code.
NRD_SETUP is initialized to “0” which leads to a violation of parameters tAR and tCLR.
The following commands are concerned; READ ID (0x90), READ STATUS (0x70), PAGE READ
(0x00, 0x30) and RANDOM DATA READ (0x05, 0xE0).
Use DataFlash Boot or external memory on EBI_NCS0.
The Real-time Timer is reset by the BootROM after each power up. This prevents using the RTT
as a backed up real-time clock.
Boot on an external memory connected on CS0 (BMS =0).
EMACB FIFO internal arbitration scheme is :
EMACB master interface releases the AHB bus between two transfers.
EMACB has the highest priority.
If EMACB RX and TX FIFOs both have pending requests, the following sequence occurs:
In case of a slow memory and/or a special operation like SDRAM refresh or SDRAM bank open-
ing, a TX underrun may occur. (latency min 960 ns).
Reduce re-arbitration time between RX & TX EMACB transfers by using internal SRAM (or
another memory slave with a short access time) to transmit buffers and descriptors.
1. Receive buffer manager write
2. Receive buffer manager read
3. Transmit data DMA read
4. Receive data DMA write
5. Transmit buffer manager read
6. Transmit buffer manager write
1. EMACB RX FIFO write (burst 4)
2. EMACB releases the AHB bus
3. The AHB matrix can grant an another master (ARM I or D for example)
4. AHB matrix re-arbitration (finishes at least the current word/halfword/byte)
5. The AHB matrix grants the EMACB
6. The EMACB TX FIFO read (burst 4)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9260
758