dspic33fj128mc706at-i-pt Microchip Technology Inc., dspic33fj128mc706at-i-pt Datasheet - Page 82
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dspic33fj128mc706at-i-pt
Manufacturer Part Number
dspic33fj128mc706at-i-pt
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC33FJ128MC706AT-I-PT.pdf
(342 pages)
- Current page: 82 of 342
- Download datasheet (5Mb)
dsPIC33FJXXXMCX06A/X08A/X10A
REGISTER 6-1:
DS70594A-page 80
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Note 1:
TRAPR
R/W-0
R/W-0
EXTR
2:
3:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
For dsPIC33FJ256MCX06A/X08A/X10A devices, this bit is unimplemented and reads back a
programmed value.
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
0 = An illegal opcode or uninitialized W Reset has not occurred
Unimplemented: Read as ‘0’
VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator is active during Sleep mode
0 = Voltage regulator goes into Standby mode during Sleep
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit
1 = WDT is enabled
0 = WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
IOPUWR
R/W-0
R/W-0
SWR
Address Pointer caused a Reset
RCON: RESET CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
SWDTEN
R/W-0
U-0
—
(2)
WDTO
R/W-0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SLEEP
R/W-0
(2)
U-0
—
(1)
(3)
R/W-0
IDLE
U-0
—
© 2009 Microchip Technology Inc.
x = Bit is unknown
R/W-1
BOR
U-0
—
VREGS
R/W-0
R/W-1
POR
bit 8
bit 0
(3)
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