dspic33fj128mc706at-i-pt Microchip Technology Inc., dspic33fj128mc706at-i-pt Datasheet - Page 203

• Manufacturer Part Number: dspic33fj128mc706at-i-pt
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

19.0
The Inter-Integrated Circuit (I
interface, provides complete hardware support for both
Slave and Multi-Master modes of the I
communication standard.
The dsPIC33FJXXXMCX06A/X08A/X10A devices have
up to two I
I2C2. Each I
pin is clock and the SDAx pin is data.
Each I
features:
• I
• I
• I
• I
• Serial clock synchronization for the I
• I
© 2009 Microchip Technology Inc.
Note:
operation.
addressing.
master and slaves.
be used as a handshake mechanism to suspend
and resume serial transfer (SCLREL control).
bus collision and will arbitrate accordingly.
2
2
2
2
2
C interface supports both master and slave
C Slave mode supports 7 and 10-bit addressing.
C Master mode supports 7 and 10-bit
C port allows bidirectional transfers between
C supports multi-master operation; it detects
2
C module ‘x’ (x = 1 or 2) offers the following key
INTER-INTEGRATED CIRCUIT
(I
2
2
This data sheet summarizes the features of
the dsPIC33FJXXXMCX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 19. “Inter-
Integrated Circuit (I
the “dsPIC33F Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
C interface modules, denoted as I2C1 and
C™)
2
C module has a 2-pin interface: the SCLx
dsPIC33FJXXXMCX06A/X08A/X10A
2
C) module, with its 16-bit
2
C™)” (DS70195) in
2
C port can
2
C serial
Preliminary
19.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
• I
For details about the communication sequence in each
of these modes, please refer to the “dsPIC30F Family
Reference Manual”.
19.2
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
I2CxRSR is the shift register used for shifting data,
whereas I2CxRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CxRCV is the receive buffer. I2CxTRN is the transmit
register to which bytes are written during a transmit
operation.
The I2CxADD register holds the slave address. A
status bit, ADD10, indicates 10-Bit Addressing mode.
The I2CxBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated.
2
2
2
C slave operation with 7-bit addressing
C slave operation with 10-bit addressing
C master operation with 7 or 10-bit addressing
2
C module can operate either as a slave or a
Operating Modes
I
2
C Registers
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
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