dspic33fj128mc706at-i-pt Microchip Technology Inc., dspic33fj128mc706at-i-pt Datasheet - Page 170

• Manufacturer Part Number: dspic33fj128mc706at-i-pt
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC33FJXXXMCX06A/X08A/X10A
REGISTER 13-1:
DS70594A-page 168
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
TON
U-0
—
The TxCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins.
TON: Timerx On bit
When T32 = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When T32 = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
Unimplemented: Read as ‘0’
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
T32: 32-Bit Timer Mode Select bit
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
Unimplemented: Read as ‘0’
TCS: Timerx Clock Source Select bit
1 = External clock from TxCK pin (on the rising edge)
0 = Internal clock (F
Unimplemented: Read as ‘0’
TGATE
R/W-0
U-0
—
TxCON (T2CON, T4CON, T6CON OR T8CON) CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
TSIDL
R/W-0
R/W-0
CY
TCKPS<1:0>
)
R/W-0
U-0
Preliminary
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
T32
U-0
—
U-0
U-0
—
—
© 2009 Microchip Technology Inc.
x = Bit is unknown
TCS
R/W-0
U-0
—
(1)
U-0
U-0
—
—
bit 8
bit 0