dspic33fj128mc706at-i-pt Microchip Technology Inc., dspic33fj128mc706at-i-pt Datasheet - Page 255

• Manufacturer Part Number: dspic33fj128mc706at-i-pt
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

23.0
dsPIC33FJXXXMCX06A/X08A/X10A devices include
several features intended to maximize application
flexibility and reliability, and minimize cost through
elimination of external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
TABLE 23-1:
© 2009 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Note 1:
Address
Note:
2:
SPECIAL FEATURES
When read, these bits will appear as ‘1’. When you write to these bits, set these bits to ‘1’.
When read, this bit returns the current programmed value.
This data sheet summarizes the features of
the dsPIC33FJXXXMCX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 23.
“CodeGuard™
Section
Diagnostics” (DS70207) and Section 25.
“Device Configuration” (DS70194) in the
“dsPIC33F Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
Name
DEVICE CONFIGURATION REGISTER MAP
24.
dsPIC33FJXXXMCX06A/X08A/X10A
FWDTEN
PWMPIN
IESO
Bit 7
—
Security”
“Programming
FCKSM<1:0>
Reserved
RBS<1:0>
RSS<1:0>
Reserved
WINDIS
HPOL
(1)
Bit 6
(DS70199),
—
(2)
and
Preliminary
PLLKEN
JTAGEN
LPOL
Bit 5
—
—
—
—
—
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
23.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The device Configuration register map is shown in
Table 23-1.
The individual Configuration bit descriptions for the
FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR and
FICD Configuration registers are shown in Table 23-2.
Note that address, 0xF80000, is beyond the user
program memory space. In fact, it belongs to the con-
figuration memory space (0x800000-0xFFFFFF) which
can only be accessed using table reads and table
writes.
The upper byte of all device Configuration registers
should always be ‘1111
appear to be NOP instructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’s to these locations
has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
WDTPRE
Bit 4
—
—
—
—
—
—
—
Configuration Bits
Bit 3
—
—
—
—
—
BSS<2:0>
SSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
GSS1
Bit 2
—
1111’. This makes them
FNOSC<2:0>
FPWRT<2:0>
DS70594A-page 253
GSS0
Bit 1
ICS<1:0>
BWRP
SWRP
GWRP
Bit 0