dspic33fj128mc706at-i-pt Microchip Technology Inc., dspic33fj128mc706at-i-pt Datasheet - Page 176

• Manufacturer Part Number: dspic33fj128mc706at-i-pt
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC33FJXXXMCX06A/X08A/X10A
15.1
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 15-1 lists the different bit settings for the Output
Compare modes. Figure 15-2 illustrates the output
compare operation for various modes. The user
TABLE 15-1:
FIGURE 15-2:
DS70594A-page 174
OCM<2:0>
(OCM<2:0> = 110 or 111)
000
001
010
011
100
101
110
111
Active-High One-Shot
Active-Low One-Shot
Output Compare Modes
(OCM<2:0> = 001)
(OCM<2:0> = 010)
(OCM<2:0> = 011)
(OCM<2:0> = 100)
(OCM<2:0> = 101)
Delayed One-Shot
Continuous Pulse
Module Disabled
Active-Low One-Shot
Active-High One-Shot
Toggle
Delayed One-Shot
Continuous Pulse
PWM without Fault Protection
PWM with Fault Protection
OUTPUT COMPARE MODES
Toggle
TMRy
PWM
OUTPUT COMPARE OPERATION
Mode
OCxRS
OCxR
Output Compare
Mode Enabled
Current output is maintained
Controlled by GPIO register
Preliminary
‘1’ if OCxR is non-zero
‘1’ if OCxR is non-zero
OCx Pin Initial State
‘0’ if OCxR is zero,
‘0’ if OCxR is zero,
Timer is Reset on
0
1
0
0
application must disable the associated timer when
writing to the Output Compare Control registers to
avoid malfunctions.
Period Match
Note:
See Section 13. “Output Compare” in
the “dsPIC33F Family Reference Manual”
(DS7029) for OCxR and OCxRS register
restrictions.
OCx rising edge
OCx falling edge
OCx rising and falling edge
OCx falling edge
OCx falling edge
No interrupt
OCFA falling edge for OC1 to OC4
OCx Interrupt Generation
© 2009 Microchip Technology Inc.
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