dspic33fj128mc706at-i-pt Microchip Technology Inc., dspic33fj128mc706at-i-pt Datasheet - Page 81

• Manufacturer Part Number: dspic33fj128mc706at-i-pt
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

6.0
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDT: Watchdog Timer Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode and Uninitialized W
A simplified block diagram of the Reset module is
shown in Figure 6-1.
FIGURE 6-1:
© 2009 Microchip Technology Inc.
Note:
Register Reset
RESET
This data sheet summarizes the features of
the dsPIC33FJXXXMCX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 8.
“Reset” (DS70192) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
MCLR
V
DD
Uninitialized W Register
RESET SYSTEM BLOCK DIAGRAM
dsPIC33FJXXXMCX06A/X08A/X10A
RESET Instruction
Regulator
Internal
Sleep or Idle
Illegal Opcode
Module
WDT
Trap Conflict
V
DD
Detect
Glitch Filter
Rise
Preliminary
BOR
POR
Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 6-1). A POR will clear all bits except for
the POR bit (RCON<0>), which is set. The user can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
Note:
Refer to the specific peripheral or CPU
section of this data sheet for register
Reset states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
SYSRST
DS70594A-page 79