atmega32c1 ATMEL Corporation, atmega32c1 Datasheet - Page 23

• Manufacturer Part Number: atmega32c1
• Description: Atmega32m1 Automotive 8-bit Avr Microcontroller With 32k/64k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

4.3.2
4.3.3
4.3.4
7647A–AVR–02/08
The EEPROM Address Registers – EEARH and EEARL
The EEPROM Data Register – EEDR
The EEPROM Control Register – EECR
• Bits 15.10 – Reserved Bits
These bits are reserved bits in the ATmega32/64/M1/C1 and will always read as zero.
• Bits 9..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
1024/2048 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0
and 1023. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7..6 – Reserved Bits
These bits are reserved bits in the ATmega32/64/M1/C1 and will always read as zero.
• Bits 5..4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be trig-
gered when writing EEWE. It is possible to program data in one atomic operation (erase the old
value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
EEAR7
EEDR7
R/W
R/W
15
R
X
R
–
7
0
7
0
7
–
0
EEAR6
EEDR6
R/W
R/W
14
R
X
–
6
0
R
6
0
6
–
0
EEAR5
EEDR5
EEPM1
R/W
R/W
R/W
13
R
X
–
5
0
5
0
5
X
EEAR4
EEDR4
EEPM0
R/W
R/W
R/W
12
R
X
–
4
0
X
4
0
4
EEAR3
EEDR3
EERIE
R/W
R/W
R/W
11
R
–
3
0
X
3
0
3
0
EEMWE
EEDR2
EEAR2
R/W
R/W
R/W
R/W
ATmega32/64/M1/C1
10
2
0
X
2
0
2
0
-
EEDR1
EEAR9
EEAR1
EEWE
R/W
R/W
R/W
R/W
1
0
1
X
X
9
1
0
EEDR0
EEAR8
EEAR0
EERE
R/W
R/W
R/W
R/W
0
0
0
0
8
0
X
X
Table
EEARH
EEARL
EEDR
EECR
4-1. While
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