atmega32c1 ATMEL Corporation, atmega32c1 Datasheet - Page 130

• Manufacturer Part Number: atmega32c1
• Description: Atmega32m1 Automotive 8-bit Avr Microcontroller With 32k/64k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

13.10.3
13.10.4
13.10.5
13.10.6
130
ATmega32/64/M1/C1
Timer/Counter1 Control Register C – TCCR1C
Timer/Counter1 – TCNT1H and TCNT1L
Output Compare Register 1 A – OCR1AH and OCR1AL
Output Compare Register 1 B – OCR1BH and OCR1BL
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
• Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
The FOCnA/FOCnB bits are only active when the WGMn3:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCRnA is written when operating in a PWM mode. When writing a logical one to the
FOCnA/FOCnB bit, an immediate compare match is forced on the Waveform Generation unit.
The OCnA/OCnB output is changed according to its COMnx1:0 bits setting. Note that the
FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the
COMnx1:0 bits that determine the effect of the forced compare.
A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB bits are always read as zero.
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers.
Registers” on page 108.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-
pare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
FOC1A
R/W
R/W
R/W
7
0
7
0
7
0
7
FOC1B
R/W
R/W
R/W
6
0
6
0
6
0
6
R/W
R/W
R
5
–
0
5
0
5
0
5
R/W
R/W
R
4
–
0
4
0
4
0
4
OCR1A[15:8]
OCR1B[15:8]
TCNT1[15:8]
OCR1A[7:0]
TCNT1[7:0]
R/W
R/W
R
3
0
3
0
3
3
–
0
R/W
R/W
2
0
2
0
2
R
2
–
0
R/W
R/W
R
1
0
1
0
1
1
–
0
See “Accessing 16-bit
R/W
R/W
R
0
0
0
0
0
0
–
0
7647A–AVR–02/08
OCR1AH
OCR1BH
TCCR1C
OCR1AL
TCNT1H
TCNT1L