atmega32c1 ATMEL Corporation, atmega32c1 Datasheet - Page 192

• Manufacturer Part Number: atmega32c1
• Description: Atmega32m1 Automotive 8-bit Avr Microcontroller With 32k/64k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

16.10.11 CAN Timer Control Register - CANTCON
16.10.12 CAN Timer Registers - CANTIML and CANTIMH
192
ATmega32/64/M1/C1
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT3 is written.
• Bit 6:4 – PHS22:0: Phase Segment 2
This phase is used to compensate for phase edge errors. This segment may be shortened by
the re-synchronization jump width. PHS2[2..0] shall be ≥1 and ≤PHS1[2..0] (c.f.
“CAN Bit Timing” on page 169
• Bit 3:1 – PHS12:0: Phase Segment 1
This phase is used to compensate for phase edge errors. This segment may be lengthened by
the re-synchronization jump width.
• Bit 0 – SMP: Sample Point(s)
This option allows to filter possible noise on TxCAN input pin.
‘SMP=1’ configuration is not compatible with ‘BRP[5:0]=0’ because TQ =
If BRP = 0, SMP must be cleared.
• Bit 7:0 – TPRSC7:0: CAN Timer Prescaler
Prescaler for the CAN timer upper counter range 0 to 255. It provides the clock to the CAN timer
if the CAN controller is enabled.
T
• Bits 15:0 - CANTIM15:0: CAN Timer Count
CAN timer counter range 0 to 65,535.
Initial Value
Read/Write
clk
Initial Value
Read/Write
Bit
Bit
CANTIM
Bit
– 0 - the sampling will occur once at the user configured sampling point - SP.
– 1 - with three-point sampling configuration the first sampling will occur two
clocks before the user configured sampling point - SP, again at one
before SP and finally at SP. Then the bit level will be determined by a majority vote of
the three samples.
CANTIM15 CANTIM14 CANTIM13 CANTIM12 CANTIM11 CANTIM10 CANTIM9 CANTIM8 CANTIMH
CANTIM7
=
T
TPRSC7
15
R
7
0
R/W
clk
7
0
IO
CANTIM6
x 8 x (CANTCON [7:0] + 1)
TPRSC6
14
R
6
0
R/W
6
0
CANTIM5
TPRSC5
and
13
R/W
R
5
0
5
0
Section 16.4.3 “Baud Rate” on page
CANTIM4
Tphs2 = Tscl x (PHS2 [2:0] + 1)
Tphs1 = Tscl x (PHS1 [2:0] + 1)
TPRSC4
R/W
12
R
4
0
4
0
TPRSC3
CANTIM3
R/W
3
0
11
R
3
0
TPRSC2
CANTIM2 CANTIM1 CANTIM0 CANTIML
R/W
2
0
10
R
2
0
TRPSC1
R/W
1
0
R
1
9
0
TPRSC0
175).
R/W
T
0
0
R
clk
0
8
0
T
clk
IO
CANTCON
.
IO
Section 16.2.3
7647A–AVR–02/08
clock
T
clk
IO