atmega163l ATMEL Corporation, atmega163l Datasheet - Page 85

• Manufacturer Part Number: atmega163l
• Description: Atmega163 8-bit Avr Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

The Two-wire Serial Interface
(Slave) Address Register –
TWAR
Two-wire Serial Interface
Modes
1142E–AVR–02/03
• Bits 7..1 – TWA: Two-wire Serial Interface (Slave) Address Register
These seven bits constitute the slave address of the Two-wire Serial Bus unit.
• Bit 0 – TWGCE: Two-wire Serial Interface General Call Recognition Enable Bit
This bit enables, if set, the recognition of the General Call given over the Two-wire Serial
Bus.
The TWAR should be loaded with the 7-bit slave address (in the seven most significant
bits of TWAR) to which the Two-wire Serial Interface will respond when programmed as
a Slave Transmitter or Receiver, and not needed in the Master modes. The LSB of
TWAR is used to enable recognition of the general call address ($00). There is an asso-
ciated address comparator that looks for the slave address (or generall call address if
enabled) in the received serial address. If a match is found, an interrupt request is
generated.
The Two-wire Serial Interface can operate in four different modes:
•
•
•
•
Data transfer in each mode of operation is shown in Figure 52 to Figure 55. These fig-
ures contain the following abbreviations:
S: START condition
R: Read bit (high level at SDA)
W: Write bit (low level at SDA)
A: Acknowledge bit (low level at SDA)
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P: STOP condition
SLA: Slave Address
In Figure 52 to Figure 55, circles are used to indicate that the Two-wire Serial Interface
Interrupt Flag is set. The numbers in the circles show the status code held in TWSR. At
these points, actions must be taken by the application to continue or complete the Two-
wire Serial Bus transfer. The Two-wire Serial Bus transfer is suspended until the Two-
wire Serial Interface Interrupt Flag is cleared by software.
The Two-wire Serial Interface Interrupt Flag is not automatically cleared by hardware
when executing the interrupt routine. Software has to clear the flag to continue the Two-
wire transfer. Also note that the Two-wire Serial Interface starts execution as soon as
this bit is cleared, so that all access to TWAR, TWDR, and TWSR must have been com-
pleted before clearing this flag.
Bit
$02 ($22)
Read/Write
Initial Value
Master Transmitter
Master Receiver
Slave Receiver
Slave Transmitter
TWA6
R/W
7
1
TWA5
R/W
6
1
TWA4
R/W
5
1
TWA3
R/W
4
1
TWA2
R/W
3
1
TWA1
R/W
2
1
ATmega163(L)
TWA0
R/W
1
1
TWGCE
R/W
0
0
TWAR
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