atmega163l ATMEL Corporation, atmega163l Datasheet - Page 84

• Manufacturer Part Number: atmega163l
• Description: Atmega163 8-bit Avr Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

The Two-wire Serial Interface
Status Register – TWSR
The Two-wire Serial Interface
Data Register – TWDR
84
ATmega163(L)
• Bit 0 – TWIE: Two-wire Serial Interface Interrupt Enable
When this bit is enabled, and the I-bit in SREG is set, the Two-wire Serial Interface inter-
rupt will be activated for as long as the TWINT Flag is high.
The TWCR is used to control the operation of the Two-wire Serial Interface. It is used to
enable the Two-wire Serial Interface, to initiate a Master access by applying a START
condition to the bus, to generate a receiver acknowledge, to generate a stop condition,
and to control halting of the bus while the data to be written to the bus are written to the
TWDR. It also indicates a write collision if data is attempted written to TWDR while the
register is inaccessible.
• Bits 7..3 – TWS: Two-wire Serial Interface Status
These five bits reflect the status of the Two-wire Serial Interface logic and the Two-wire
Serial Bus.
• Bits 2..0 – Res: Reserved bits
These bits are reserved in ATmega163 and will always read as zero
The TWSR is read only. It contains a status code which reflects the status of the Two-
wire Serial Interface logic and the Two-wire Serial Bus. There are 26 possible status
codes. When TWSR contains $F8, no relevant state information is available and no
Two-wire Serial Interface interrupt is requested. A valid status code is available in
TWSR one CPU clock cycle after the Two-wire Serial Interface Interrupt Flag (TWINT) is
set by hardware and is valid until one CPU clock cycle after TWINT is cleared by soft-
ware. Table 32 to Table 36 give the status information for the various modes.
• Bits 7..0 – TWD: Two-wire Serial Interface Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte
received on the Two-wire Serial Bus.
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the
TWDR contains the last byte received. It is writeable while the Two-wire Serial Interface
is not in the process of shifting a byte. This occurs when the Two-wire Serial Interface
Interrupt Flag (TWINT) is set by hardware. Note that the Data Register cannot be initial-
ized by the user before the first interrupt occurs. The data in TWDR remain stable as
long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted
in. TWDR always contains the last byte present on the bus, except after a wake up from
ADC Noise Reduction mode, Power-down mode, or Power-save mode by the Two-wire
Serial Interface interrupt. For example, in the case of a lost bus arbitration, no data is
lost in the transition from Master to Slave. Handling of the ACK Flag is controlled auto-
matically by the Two-wire Serial Interface logic, the CPU cannot access the ACK bit
directly.
Bit
$01 ($21)
Read/Write
Initial Value
Bit
$03 ($23)
Read/Write
Initial Value
TWS7
TWD7
R/W
R
7
1
7
1
TWS6
TWD6
R/W
R
6
1
6
1
TWS5
TWD5
R/W
5
R
1
5
1
TWD4
TWS4
R/W
R
4
1
4
1
TWS3
TWD3
R/W
R
3
1
3
1
TWD2
R/W
R
2
–
0
2
1
TWD1
R/W
R
1
–
0
1
1
TWD0
R/W
0
–
R
0
0
1
1142E–AVR–02/03
TWSR
TWDR