atmega163l ATMEL Corporation, atmega163l Datasheet - Page 82

• Manufacturer Part Number: atmega163l
• Description: Atmega163 8-bit Avr Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

The Two-wire Serial Interface
Bit Rate Register – TWBR
The Two-wire Serial Interface
Control Register – TWCR
82
ATmega163(L)
• Bits 7..0 – Two-wire Serial Interface Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a
frequency divider which generates the SCL clock frequency in the Master modes
according to the following equation:
•
•
•
•
Note:
TWBR should be set to a value higher than seven to ensure correct Two-wire Serial Bus
functionality. The bus alignment adjustion is automatically inserted by the Two-wire
Serial Interface, and ensures the validity of setup and hold times on the bus for any
TWBR value higher than seven. This adjustment may vary from 200 ns to 600 ns
depending on bus loads and drive capabilities of the devices connected to the bus.
• Bit 7 – TWINT: Two-wire Serial Interface Interrupt Flag
This bit is set by hardware when the Two-wire Serial Interface has finished its current
job and expects application software response. If the I-bit in the SREG and TWIE in the
TWCR Register are set (one), the MCU will jump to the Interrupt Vector at address $22.
While the TWINT Flag is set, the bus SCL clock line low period is stretched. The TWINT
Flag must be cleared by software by writing a logic one to it. Note that this flag is not
automaticaly cleared by hardware when executing the interrupt routine. Also note that
clearing this flag starts the operation of the Two-wire Serial Interface, so all accesses to
the Two-wire Serial Interface Address Register – TWAR, Two-wire Serial Interface Sta-
tus Register – TWSR, and Two-wire Serial Interface Data Register – TWDR must be
complete before clearing this flag.
Bit
$00 ($20)
Read/Write
Initial Value
Bit
$36 ($56)
Read/Write
Initial Value
Bit Rate = SCL frequency
f
TWBR = Contents of the Two-wire Serial Interface Bit Rate Register
t
CK
A
= Bus alignment adjustion
= CPU Clock frequency
Both the Receiver and the Transmitter can stretch the low period of the SCL line when
waiting for user response, thereby reducing the average bit rate.
TWBR7
TWINT
R/W
R/W
7
0
7
0
TWBR6
TWEA
R/W
R/W
6
0
6
0
Bit Rate
TWBR5
TWSTA
R/W
R/W
5
0
5
0
=
TWBR4
TWSTO
---------------------------------------------------------- -
16
R/W
R/W
4
0
4
0
+
2(TWBR) + t
TWBR3
TWWC
R/W
f
CK
R
3
0
3
0
TWBR2
TWEN
R/W
R/W
A
2
0
2
0
f
CK
TWBR1
R/W
R
1
0
1
–
0
TWBR0
TWIE
R/W
R/W
0
0
0
0
1142E–AVR–02/03
TWBR
TWCR