atmega163l ATMEL Corporation, atmega163l Datasheet - Page 33

• Manufacturer Part Number: atmega163l
• Description: Atmega163 8-bit Avr Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

External Interrupts
1142E–AVR–02/03
Timer/Counter2 Overflow Interrupt is executed. In up/down PWM mode, this bit is set
when Timer/Counter2 changes counting direction at $00.
• Bit 5 – ICF1: Input Capture Flag1
The ICF1 bit is set (one) to Flag an Input Capture Event, indicating that the
Timer/Counter1 value has been transferred to the Input Capture Register – ICR1. ICF1
is cleared by hardware when executing the corresponding Interrupt Handling Vector.
Alternatively, ICF1 is cleared by writing a logic one to the flag.
• Bit 4 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when a Compare Match occurs between the Timer/Counter1
and the data in OCR1A – Output Compare Register 1A. OCF1A is cleared by hardware
when executing the corresponding Interrupt Handling Vector. Alternatively, OCF1A is
cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A
(Timer/Counter1 Compare Match Interrupt A Enable), and the OCF1A are set (one), the
Timer/Counter1A Compare Match Interrupt is executed.
• Bit 3 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when a Compare Match occurs between the Timer/Counter1
and the data in OCR1B – Output Compare Register 1B. OCF1B is cleared by hardware
when executing the corresponding Interrupt Handling Vector. Alternatively, OCF1B is
cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B
(Timer/Counter1 Compare Match Interrupt B Enable), and the OCF1B are set (one), the
Timer/Counter1B Compare Match Interrupt is executed.
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding Interrupt Handling Vector. Alternatively,
TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1
( Time r /C o u n te r1 O ve r flo w In te r ru p t En a b le ), a n d TO V 1 a r e se t ( o ne ) , th e
Timer/Counter1 Overflow Interrupt is executed. In up/down PWM mode, this bit is set
when Timer/Counter1 changes counting direction at $0000.
• Bit 1 – Res: Reserved Bit
This bit is a reserved bit in the ATmega163 and the read value is undefined.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding Interrupt Handling Vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0
( Time r /C o u n te r0 O ve r flo w In te r ru p t En a b le ), a n d TO V 0 a r e se t ( o ne ) , th e
Timer/Counter0 Overflow interrupt is executed.
The external interrupts are triggered by the INT0 and INT1 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs.
This feature provides a way of generating a software interrupt. The external interrupts
can be triggered by a falling or rising edge or a low level. This is set up as indicated in
the specification for the MCU Control Register – MCUCR. When the external interrupt is
enabled and is configured as level triggered, the interrupt will trigger as long as the pin is
held low.
ATmega163(L)
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