atmega163l ATMEL Corporation, atmega163l Datasheet - Page 31

• Manufacturer Part Number: atmega163l
• Description: Atmega163 8-bit Avr Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

The General Interrupt Flag
Register – GIFR
The Timer/Counter Interrupt
Mask Register – TIMSK
1142E–AVR–02/03
• Bits 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATmega163 and always read as zero.
• Bit 7 – INTF1: External Interrupt Flag1
When an edge on the INT1 pin triggers an interrupt request, the correspnding Interrupt
Flag, INTF1, becomes set (one). If the I-bit in SREG and the corresponding Interrupt
Enable bit, INT1 in GIMSK are set (one), the MCU will jump to the Interrupt Vector. The
Flag is cleared when the interrupt routine is executed. Alternatively, the Flag can be
cleared by writing a logical one to it. This Flag is always cleared when INT1 is config-
ured as a level interrupt.
• Bit 6 – INTF0: External Interrupt Flag0
When an event on the INT0 pin triggers an interrupt request, the corresponding Interrupt
Flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding Interrupt
Enable bit, INT0 in GIMSK are set (one), the MCU will jump to the Interrupt Vector. The
Flag is cleared when the interrupt routine is executed. Alternatively, the Flag can be
cleared by writing a logical one to it. This Flag is always cleared when INT0 is config-
ured as a level interrupt.
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the ATmega163 and always read as zero.
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match Interrupt is enabled. The corresponding interrupt (at
vector $006) is executed if a Compare Match in Timer/Counter2 occurs, i.e., when the
OCF2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$008) is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set
in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt
Bit
$3A ($5A)
Read/Write
Initial Value
Bit
$39 ($59)
Read/Write
Initial Value
INTF1
OCIE2
R/W
R/W
7
0
7
0
INTF0
R/W
6
0
TOIE2
R/W
6
0
R
5
–
0
TICIE1
R/W
5
0
4
–
R
0
OCIE1A
R/W
4
0
OCIE1B
R
3
–
0
R/W
3
0
TOIE1
R
R/W
2
–
0
ATmega163(L)
2
0
R
1
–
0
R
1
–
0
TOIE0
R/W
R
0
–
0
0
0
GIFR
TIMSK
31