atmega163l ATMEL Corporation, atmega163l Datasheet - Page 35

• Manufacturer Part Number: atmega163l
• Description: Atmega163 8-bit Avr Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Sleep Modes
Idle Mode
ADC Noise Reduction Mode
1142E–AVR–02/03
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-Flag and the
corresponding interrupt mask are set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 9. The value on the INT0 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer
than one clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. If low level interrupt is selected, the low level must be held until
the completion of the currently executing instruction to generate an interrupt.
Table 9. Interrupt 0 Sense Control
To enter any of the four sleep modes, the SE bit in MCUCR must be set (one) and a
SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUCR Register
select which sleep mode (Idle, ADC Noise Reduction, Power-down, or Power-save) will
be activated by the SLEEP instruction. See Table 7 for a summary. If an enabled inter-
rupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then
halted for four cycles, executes the interrupt routine, and resumes execution from the
instruction following SLEEP. The contents of the Register File, SRAM, and I/O memory
are unaltered when the device wakes up from sleep. If a Reset occurs during sleep
mode, the MCU wakes up and executes from the Reset Vector.
When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing SPI, UART, Analog Comparator, ADC, Two-wire
Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue oper-
ating (if enabled). This enables the MCU to wake up from external triggered interrupts
as well as internal ones like the Timer Overflow and UART Receive Complete interrupts.
If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and Sta-
tus Register – ACSR. This will reduce power consumption in Idle Mode. If the ADC is
enabled, a conversion starts automatically when this mode is entered.
When the SM1/SM0 bits are set to 01, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external inter-
rupts, the Two-wire Serial Interface address watch, Timer/Counter2 and the Watchdog
to continue operating (if enabled). This improves the noise environment for the ADC,
enabling higher resolution measurements. If the ADC is enabled, a conversion starts
automatically when this mode is entered. Apart from the ADC Conversion Complete
interrupt, only an External Reset, a Watchdog Reset (if enabled), a Brown-out Reset, a
Two-wire Serial Interface address match interrupt, or an external level interrupt can
wake up the MCU from ADC Noise Reduction Mode. A Timer/Counter2 Output Com-
pare or overflow event will wake up the MCU, but will not generate an interrupt unless
Timer/Counter2 is clocked asynchronously.
In future devices this is subject to change. It is recommended for future code compatibil-
ity to disable Timer/Counter2 interrupts during ADC Noise Reduction mode if the
Timer/Counter2 is clocked synchronously.
ISC01
0
0
1
1
ISC00
0
1
0
1
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
ATmega163(L)
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