atmega163l ATMEL Corporation, atmega163l Datasheet - Page 30

• Manufacturer Part Number: atmega163l
• Description: Atmega163 8-bit Avr Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Interrupt Response Time
The General Interrupt Mask
Register – GIMSK
30
ATmega163(L)
If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the Global
Interrupt Enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for
as long as the interrupt condition is present.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. After four clock cycles the Program Vector address for the actual interrupt
handling routine is executed. During this four clock cycle period, the Program Counter
(13 bits) is pushed onto the Stack. The vector is normally a jump to the interrupt routine,
and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-
cycle instruction, this instruction is completed before the interrupt is served. If an inter-
rupt occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by four clock cycles.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack
Pointer is incremented by two, and the I Flag in SREG is set. When AVR exits from an
interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is activated. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity
on the pin will cause an interrupt request even if INT1 is configured as an output. The
corresponding interrupt of External Interrupt Request 1 is executed from program mem-
ory address $004. See also “External Interrupts”.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is activated. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU General Control Register (MCUCR) define whether the external
interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT0 is configured as an output. The corre-
sponding interrupt of External Interrupt Request 0 is executed from Program Memory
address $002. See also “External Interrupts.”
• Bits 5 – Res: Reserved Bits
This bit is reserved in the ATmega163 and the read value is undefined.
Bit
$3B ($5B)
Read/Write
Initial Value
INT1
R/W
7
0
INT0
R/W
6
0
R
5
–
x
4
–
R
0
R
3
–
0
R
2
–
0
R
1
–
0
1142E–AVR–02/03
R
0
–
0
GIMSK