atmega163l ATMEL Corporation, atmega163l Datasheet - Page 73

• Manufacturer Part Number: atmega163l
• Description: Atmega163 8-bit Avr Microcontroller With 16k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Multi-processor
Communication Mode
1142E–AVR–02/03
Figure 47. Sampling Received Data
Note:
When the stop bit enters the Receiver, the majority of the three samples must be one to
accept the stop bit. If two or more samples are logical zeros, the Framing Error (FE)
Flag in the UART Status Register (USR) is set. Before reading the UDR Register, the
user should always check the FE bit to detect Framing Errors.
Whether or not a valid stop bit is detected at the end of a character reception cycle, the
data is transferred to UDR and the RXC Flag in USR is set. UDR is in fact two physically
separate registers, one for transmitted data and one for received data. When UDR is
read, the Receive Data Register is accessed, and when UDR is written, the Transmit
Data Register is accessed. If 9-bit data word is selected (the CHR9 bit in the UART Con-
trol Register, UCR is set), the RXB8 bit in UCR is loaded with bit nine in the Transmit
Shift Register when data is transferred to UDR.
If, after having received a character, the UDR Register has not been read since the last
receive, the OverRun (OR) Flag in UCR is set. This means that the last data byte shifted
into to the Shift Register could not be transferred to UDR and has been lost. The OR bit
is buffered, and is updated when the valid data byte in UDR is read. Thus, the user
should always check the OR bit when reading the UDR Register in order to detect any
overruns if the baud rate is high or CPU load is high.
When the RXEN bit in the UCR Register is cleared (zero), the receiver is disabled. This
means that the PD0 pin can be used as a general I/O pin. When RXEN is set, the UART
Receiver will be connected to PD0, which is forced to be an input pin regardless of the
setting of the DDD0 bit in DDRD. When PD0 is forced to input by the UART, the
PORTD0 bit can still be used to control the pull-up resistor on the pin.
When the CHR9 bit in the UCR Register is set, transmitted and received characters are
9-bit long plus start and stop bits. The ninth data bit to be transmitted is the TXB8 bit in
UCR Register. This bit must be set to the wanted value before a transmission is initated
by writing to the UDR Register. The 9th data bit received is the RXB8 bit in the UCR
Register.
It is important that the Status Register (USR) always is read before the Data Register
(UDR). The Data Register should be read only once for each received byte. Otherwise,
the Status Register (USR) might get updated with incorrect values.
The Multi-Processor Communication mode enables several Slave MCUs to receive data
from a Master MCU. This is done by first decoding an address byte to find out which
MCU has been addressed. If a particular Slave MCU has been addressed, it will receive
the following data bytes as normal, while the other Slave MCUs will ignore the data
bytes until another address byte is received.
For an MCU to act as a Master MCU, it should enter 9-bit transmission mode (CHR9 in
UCSRB set). The ninth bit must be one to indicate that an address byte is being trans-
mitted, and zero to indicate that a data byte is being transmitted.
For the Slave MCUs, the mechanism appears slightly differently for 8-bit and 9-bit
reception mode. In 8-bit reception mode (CHR9 in UCSRB cleared), the stop bit is one
for an address byte and zero for a data byte. In 9-bit reception mode (CHR9 in UCSRB
1. This figure is not valid when the UART speed is doubled. See “Double Speed Trans-
mission” on page 78 for a detailed description.
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ATmega163(L)
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