aduc7032 Analog Devices, Inc., aduc7032 Datasheet - Page 61

• Manufacturer Part Number: aduc7032
• Description: Microconverter Integrated, Precision Battery Sensor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
ADC Normal Power Mode
In Normal Mode, the Current and Voltage/Temperature
channels are fully enabled. The ADC modulator clock is
512KHz and enables the ADCs to provide regular conversion
results at a rate of between 4Hz and 8KHz (see ADCFLT). Both
channels are under full control of the MCU and can be
reconfigured at any time. The default ADC update rate for all
channels in this mode is 1.0kHz
It is worth emphasizing that I-ADC and V/T-ADC channels
can be configured to initiate periodic, normal power mode,
high accuracy, single conversion cycles before returning to
ADC full power-down mode. This flexibility is facilitated under
full MCU control via the ADCMDE MMR and ensures that
continuous periodic monitoring of battery current, voltage and
temperature settings is feasible while ensuring the average dc
current consumption is minimized.
In ADC Normal Mode, the PLL must not be powered down.
ADC Low Power Mode
In ADC Low Power mode, the I-ADC is enabled in a reduced
power and reduced accuracy configuration. The ADC
modulator clock is now driven directly from the on-chip
131KHz low power oscillator, which allows the ADC to be
configured at update rates as low as 1Hz(ADCFLT). The gain of
the ADC in this mode is fixed at 128.
All of the ADC peripheral functions (result counter, digital
comparator and accumulator) described earlier in normal
power mode can still be enabled in low power mode.
Typically, in Low Power Mode, the I-ADC only, is configured
to run at a low update rate, continuously monitoring battery
current. The MCU will be in power-down mode and will only
be woken up when the I-ADC interrupts the MCU. This would
happen after the I-ADC detects a current conversion or an
accumulated current value has risen beyond a pre-programmed
threshold, set-point or a set number of conversions.
It is also possible to select either the ADC Normal Mode
Voltage Reference of the ADC Low Power Mode Voltage
Reference via ADCMDE[5].
ADC Low Power-Plus Mode
In Low Power-Plus mode, the I-ADC channel is enabled in a
mode almost identical to low-power mode(ADCMDE[4:3]).
However, in this mode, the I-ADC gain is fixed at 512 and the
ADC consumes an additional 200uA (approx.) to yield
improved noise performance relative to the low-power mode
setting.
Again, all of the ADC peripheral functions (result counter,
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digital comparator and accumulator) described earlier in
normal power mode can still be enabled in Low Power-Plus
mode.
As in Low Power Mode, the I-ADC only, is configured to run at
a low update rate, continuously monitoring battery current.
The MCU will be in power-down mode and will only be woken
up when the I-ADC interrupts the MCU. This would happen
after the I-ADC detects a current conversion result or an
accumulated current value has risen beyond a pre-programmed
threshold or set-point.
It is also possible to select either the ADC Normal Mode
Voltage Reference of the ADC Low Power Mode Voltage
Reference via ADCMDE[5].
ADC Sinc3 Digital Filter Response
The overall frequency response on all ADuC7032s ADCs is
dominated by the low pass filter response of the on-chip Sinc3
digital filters. The Sinc3 filters are used to decimate the ADC
sigma-delta modulator output data bit-stream to generate a
valid 16-bit data result. The digital filter response is identical
for all ADCs and is configured via the 16-bit ADC Filter
(ADCFLT) register which determines the overall throughput
rate of the ADCs. The noise resolution of the ADCs is
determined by the programmed ADC throughput rate. In the
case of the Current Channel ADC, the noise resolution will be
determined by throughput rate and selected gain.
The overall frequency response and the ADC through-put is
dominated by the configuration of the Sinc3 Filter Decimation
Factor (SF) bits (ADCFLT[6:0]) and the Averaging Factor (AF)
bits(ADCFLT[13:8]). Due to limitations on the digital filter
internal data-path, there are some limitations on the allowable
combinations
AF(Averaging Factor) that can be used to generate a required
ADC output rate. This restriction limits the minimum ADC
update in Normal Power Mode to 4Hz or 1Hz in Low Power
Mode. The calculation of the ADC through-put rate is detailed
in the ADCFLT bit designations table and the restrictions on
allowable combinations of AF and SF values are outlined again
in Table 31
SF
<= 31
AF Range
127
63
Table 31 : Allowable Combinations of SF and AF
of
SF(Sinc3
0
Decimation
1 to 7
ADuC7032
Factor)
8-63
and