aduc7032 Analog Devices, Inc., aduc7032 Datasheet - Page 40

• Manufacturer Part Number: aduc7032
• Description: Microconverter Integrated, Precision Battery Sensor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
MEMORY MAPPED REGISTERS
The Memory Mapped Register (MMR) space is mapped into
the top 4kBytes of the MCU memory space and accessed by
indirect addressing, load and store commands, through the
ARM7 banked registers. An outline of the ADuC7032s Memory
Mapped Register Bank is shown in Figure 14.
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers except the ARM7 core
registers (described in ARM Registers) reside in the MMR area.
As can be seen from the detailed MMR map in Table 17, the
MMR data widths vary from 1 Byte (8 bits) to 4 Bytes (32 bits).
The ARM7 core can access any of the MMRs (single byte or
multiple byte width registers) with a 32 bit read or write access.
The resultant read for example, aligned per ‘little endian’
format described earlier. However, errors will result if the
ARM7 core tries to access 4 Byte (32 bit) MMRs with a 16-bit
access. In the case of a (16-bit) write access to a 32-bit MMR,
the (upper) 16 most significant bits will be written as 0’s. More
obviously, in the case of a 16-bit read access to a 32-bit MMR,
only 16 of the MMR bits can be read.
Rev. PrD | Page 40 of 128
0xFFFFFFFF
0xFFFF0D50
0xFFFF0D00
0xFFFF0A14
0xFFFF0A00
0xFFFF079C
0xFFFF044C
0xFFFF0E00
0xFFFF1000
0xFFFF0894
0xFFFF0880
0xFFFF0810
0xFFFF0800
0xFFFF0780
0xFFFF0730
0xFFFF0700
0xFFFF0568
0xFFFF0500
0xFFFF0400
0xFFFF0394
0xFFFF0380
0xFFFF0370
0xFFFF0360
0xFFFF0350
0xFFFF0340
0xFFFF0334
0xFFFF0320
0xFFFF0318
0xFFFF0300
0xFFFF0244
0xFFFF0220
0xFFFF0110
0xFFFF0000
Figure 14: Top Level MMR Map
OSCILLATOR CONTROL
GENERAL PURPOSE
GENERAL PURPOSE
SYSTEM CONTROL
FLASH CONTROL
HV INTERFACE
CONTROLLER
SERIAL TEST
REMAP AND
HARDWARE
WATCHDOG
INTERFACE
INTERFACE
INTERRUPT
WAKE UP
PLL AND
LIN/BSD
TIMER 4
TIMER 3
TIMER 2
TIMER 1
TIMER 0
UART
GPIO
ADC
SPI
ADuC7032