aduc7032 Analog Devices, Inc., aduc7032 Datasheet - Page 119

• Manufacturer Part Number: aduc7032
• Description: Microconverter Integrated, Precision Battery Sensor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
LIN Hardware Break Timer1 Register :
Name :
Address :
Default Value :
Access :
Function :
LIN HARDWARE INTERFACE
LIN Frame Protocol
The LIN frame protocol is broken into 4 main categories:
Break Symbol
SYNC Byte
Protected Identifier
Data Bytes
LHSVAL1
0xFFFF0790
0x000(read) or 0x047(write)
Read/Write
When user code reads this location, the 12-bit value returned is the value of the internal LIN break timer, which is
clocked directly from the on-chip low power (131KHz) oscillator and times the LIN Break pulse. A negative edge on
the LIN bus or user code reading the LHSVAL1 will result in the timer and the register contents being reset to 0.
When user code writes to this location, the 12-bit value is actually written not to the LIN Break timer but to a LIN
In LIN mode of operation the value in the compare register is continuously compared to the break timer value. A LIN
Break interrupt (IRQEN[7] and LHSSTA[0]) is generated when the timer value reaches the compare value. After the
Break Condition interrupt, the LIN Break timer continues to count until the rising edge of the Break signal. If a
rising edge is not detected and the 12-bit timer overflows (4096 X 1/131KHz= 31msecs), a Break Field Error Interrupt
(IRQEN[7] and LHSSTA[4]) will be generated. By default, the value in the compare register is 0x47, this corresponds
to 11 X Bit periods i.e. the minimum pulse width for a LIN break pulse at 20kbps. For different baud rates, this value
may be changed by writing to. It is also important to note that if a valid break interrupt is not received then
subsequent Sync pulse timing via LHSVAL0 register will not occur.
Break Compare register.
BREAK
13T
> = 14T
BIT
BIT
>1T
BIT
STA S0
2T
Figure 39 : LIN Interface Timing
BIT
Rev. PrD | Page 119 of 128
SYNC
S1
2T
BIT
8T
S2
BIT
S3
2T
BIT
The format of the frame header, Break, Synchronization Byte
and Protected Identifier are shown in Figure 39. Essentially, the
embedded UART, LIN Hardware Synchronization logic and the
high voltage transceiver interface all combine on-chip to
support and manage LIN based transmissions and receptions.
S4
S5
2T
BIT
S6
S7 STO
PROTECTED ID
ADuC7032