aduc7032 Analog Devices, Inc., aduc7032 Datasheet - Page 28

• Manufacturer Part Number: aduc7032
• Description: Microconverter Integrated, Precision Battery Sensor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Interrupt latency
The worst case latency for an FIQ consists of the longest time
the request can take to pass through the synchronizer, plus the
time for the longest instruction to complete (the longest
instruction is an LDM) which loads all the registers including
the PC, plus the time for the data abort entry, plus the time for
FIQ entry. At the end of this time, the ARM7TDMI will be
executing the instruction at 0x1C (FIQ interrupt vector
address). The maximum total time is 50 processor cycles, which
is just over 2.44 S in a system using a continuous 20.48MHz
processor clock. The maximum IRQ latency calculation is
similar, but must allow for the fact that FIQ has higher priority
and could delay entry into the IRQ handling routine for an
arbitrary length of time. This time may be reduced to 42 cycles
if the LDM command is not used, some compilers have an
option to compile without using this command. Another option
is to run the part in THUMB mode where this is reduced to 22
cycles.
The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time the request can take through
the synchronizer plus the time to enter the exception mode.
Note that the ARM7TDMI will initially (1
ARM (32-bit) mode when an exception occurs. The user may
immediately switch from ARM mode to Thumb mode if
required, e.g. when executing interrupt service routines.
MEMORY ORGANISATION
The ARM7, a Von Neumann architecture, MCU core sees
memory as a linear array of 2 32 byte locations. As shown in
Figure 11, the ADuC7032 maps this into 4 distinct user areas
namely, a re-mappable memory area, an SRAM area, a Flash/EE
area and a Memory Mapped Register (MMR) area.
The first 96kBytes of this memory space is used as an area into
which the on-chip Flash/EE or SRAM can be remapped. A
second 4kByte area at the top of the memory map is used to
locate the Memory Mapped Registers (MMR), through which
all on-chip peripherals are configured and monitored. The
remaining 2 areas of memory are constituted as 6kByte of
SRAM and 96kByte of On-Chip Flash/EE memory. 94kByte of
On-Chip Flash/EE memory are available to the user, and the
remaining 2kBytes are reserved for the on-chip Kernel. These
areas are described in more detail below.
Any access, either reading or writing, to an area not defined in
the memory map will result in a Data Abort exception.
st
instruction) run in
Rev. PrD | Page 28 of 128
Memory Format
The ADuC7032 memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address.
SRAM
6kBytes of SRAM are available to the user, organized as 1536 X
32 bits, i.e. 1536Words, which is located at 0x40000. The RAM
space can be used as data memory and also as a volatile
program space.
ARM code can run directly from SRAM at full clock speed
given that the SRAM array is configured as a 32-bit wide
memory array.
SRAM is read/writeable in 8/16/32 bit segments.
BIT 31
FFFF0000h
00080000h
00040000h
00000000h
BYTE 3
B
7
3
.
.
.
Figure 11: ADuC7032 Memory Map
FFFF0FFFh
BYTE 2
00097FFFh
Figure 10: Little Endian Format
00417FFh
0017FFFh
A
6
2
.
.
.
32 BITS
BYTE 1
RESERVED
MMRs
RESERVED
FLASH/EE
RESERVED
SRAM
RESERVED
RE-MAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
9
5
1
.
.
.
BYTE 0
8
4
0
.
.
.
BIT 0
0xFFFFFFFFh
0x00000004h
0x00000000h
ADuC7032