adm1075-2aruz-rl7 Analog Devices, Inc., adm1075-2aruz-rl7 Datasheet - Page 7

• Manufacturer Part Number: adm1075-2aruz-rl7
• Description: −48 V Hot Swap Controller And Digital Power Monitor With Pmbus Interface
• Manufacturer: Analog Devices, Inc.

Data Sheet
Parameter
SOFT START
TIMER
PLIM
DRAIN
ADC_AUX/ADC_V
SHDN PIN
RESTART PIN
SPLYGD PIN
LATCH PIN
GPO1/ALERT1/CONV PIN
Timer Pull-Up Current (POR), I
Timer Pull-Up Current (OC Fault), I
Timer Pull-Down Current (Retry), I
Timer Retry/OC Fault Current Ratio
Timer Pull-Down Current (Hold), I
Timer High Threshold, V
Timer Low Threshold, V
PLIM Active Threshold
Input Current, I
Minimum Current Clamp, V
DRAIN Voltage at Which PWRGD Asserts
Input Current
Input High Voltage, V
Input Low Voltage, V
Glitch Filter
Internal Pull-Up Current
SS Pull-Up Current, I
Default V
SS Pull-Down Current
Input High Voltage, V
Input Low Voltage, V
Glitch Filter
Internal Pull-Up Current
Output Low Voltage, V
Leakage Current
Output Low Voltage, V
Leakage Current
Output Low Voltage, V
Total Response Time
SENSECL
Limit
PLIM
SS
IL
IL
IH
IH
OL_LATCH
OL_LATCH
OL_GPO1
TIMERL
TIMERH
ICLAMP
TIMERUPPOR
TIMERDNHOLD
TIMERDNRT
TIMERUPFLT
Min
180
610
7
45
−11.5
0.6
1.2
−4
−63
1.7
0.98
0.03
0.08
75
1.9
1.1
1.1
Typ
−10
1.25
2.5
100
−3
−60
2
3.33
100
1.0
0.05
0.09
100
2
1
8
1
8
Rev. 0 | Page 7 of 52
Max
300
950
13
60
−8.5
1.9
3.8
−2
−57
2.3
1.02
0.07
0.1
100
125
2.1
100
0.8
0.8
0.4
1.5
100
1
0.4
1.5
100
1
0.4
1.5
μA
Unit
ns
ns
μs
μs
μA
mV
mV
μA
μA
μA
%
μA
V
V
V
nA
mV
V
nA
V
V
μs
μA
V
V
μs
μA
V
V
nA
μA
V
V
nA
μA
V
V
Test Conditions/Comments
Initial power-on reset; V
Overcurrent fault; 0.05 V ≤ V
After a fault when GATE is off; V
Holds TIMER at 0 V when inactive; V
Pull-up to VIN
Pull-up to VIN
V
optional select through PMBus
V
default at power-up
V
optional select through PMBus
V
optional select through PMBus
V
When V
V
When V
V
V
Defines the limits of the autoretry duty cycle
V
V
V
allowed current control
I
0 V ≤ V
I
I
V
V
I
I
V
V
I
I
DRAIN
SPLYGD
SPLYGD
LATCH
LATCH
GPO
GPO
ISET
ISET
ISET
ISET
SS
SS
SS
SS
ISET
PLIM
PLIM
SPLYGD
SPLYGD
LATCH
LATCH
= 0V
= 0 V;
= 0 V;
= 1 V
= 1 mA
= 5 mA
> 1.65 V; V
> 1.65 V; V
> 1.65 V; V
> 1.65 V; V
> 1.65 V
≤ 1 V
= 1.2 V; V
≤ 50 μA
= 1 mA
= 5 mA
= 1 mA
= 5 mA
≤ 2 V; LATCH pin disabled
≤ 14 V; LATCH pin disabled
≤ 2 V; SPLYGD pin disabled
≤ 14 V; SPLYGD pin disabled
ADC
SENSE
SENSE
ADM1075-1
ADM1075-2
≤ 1.5 V
reaches this level, I
reaches this level, I
SENSE_IMIN
SS
SS
SS
SS
≥ 2 V; V
≥ 2 V; V
≥ 2 V; V
≥ 2 V; V
= (V
only (gain = 50)
only (gain = 25)
TIMER
SENSE
SENSE
SENSE
SENSE
ICLAMP
= 0.5 V
step from 36 mV to 104 mV;
step from 36 mV to 104 mV;
step from 36 mV to 104 mV;
step from 36 mV to 104 mV;
TIMER
SS
SS
÷ gain) = minimum
TIMER
≤ 1 V
is enabled, ramping;
is enabled, ramping;
= 0.5 V
TIMER
= 0.5 V
ADM1075