adm1075-2aruz-rl7 Analog Devices, Inc., adm1075-2aruz-rl7 Datasheet - Page 36

• Manufacturer Part Number: adm1075-2aruz-rl7
• Description: −48 V Hot Swap Controller And Digital Power Monitor With Pmbus Interface
• Manufacturer: Analog Devices, Inc.

ADM1075
ADM1075 ALERT PIN BEHAVIOR
The
one or more fault/warning conditions can be indicated to an
external device.
FAULTS AND WARNINGS
A PMBus fault on the
analog event and causes a change in state in the hot swap output,
turning it off. The three defined fault sources are as follows:
•
•
•
Faults are continuously monitored, and, as long as power is
applied to the device, they cannot be disabled. When a fault
occurs, a corresponding status bit is set in one or more
STATUS_xxx registers.
A value of 1 in a status register bit field always indicates a fault
or warning condition. Fault and warning bits in the status
registers are latched when set to 1. To clear a latched bit to 0—
provided that the fault condition is no longer active—use the
CLEAR_FAULTS command or use the OPERATION command
to turn the hot swap output off and then on again.
The latched status registers provide fault recording functionality.
In the event of a fault, the HS_SHUTDOWN_CAUSE bits in
the manufacturing specific status register (0x80) can be used to
identify the fault source (UV, OV, or OC). Other status registers
can also be checked for more fault and warning information.
A warning is less severe than a fault and never causes a change
in the state of the hot swap controller. The eight sources of a
warning are defined as follows:
•
•
•
•
•
•
•
•
•
GENERATING AN ALERT
A host device can periodically poll the
status commands to determine whether a fault/warning is
active. However, this polling is very inefficient in terms of
software and processor resources. The
GPOx/ ALERTx output pins that can be used to generate
interrupts to a host processor, GPO1/ ALERT1 /CONV and
GPO2/ ALERT2 .
ADM1075
Undervoltage (UV) event detected on the UVH and UVL
pins
Overvoltage (OV) event detected on the OV pin
Overcurrent (OC) event that causes a hot swap timeout
CML: a communications error occurred on the I
HS timer was active (HSTA): the current regulation was
active but does not necessarily shut the system down
IOUT OC warning from the ADC
IOUT Warning 2 from the ADC
VIN UV warning from the ADC
VIN OV warning from the ADC
VAUX UV warning from the ADC
VAUX OV warning from the ADC
PIN OP warning from the ADC
provides a very flexible alert system, whereby
ADM1075
is always generated due to an
ADM1075
ADM1075
has two
using the
2
C bus
Rev. 0 | Page 36 of 52
By default, at power-up, the open-drain GPOx/ ALERTx
outputs are high impedance; therefore, the pins can be pulled
high through resistors. No faults or warnings are enabled on the
GPO2/ ALERT2 pin at power-up; the user must explicitly enable
the faults or warnings to be monitored. The FET health bad
warning is active by default on the GPO1/ ALERT1 /CONV pin
at power-up.
Any one or more of the faults and warnings listed in the Faults
and Warnings section can be enabled and cause an alert, making
the corresponding GPOx/ ALERTx pin active. By default, the
active state of a GPOx/ ALERTx pin is low.
For example, to use GPO1/ ALERT1 /CONV to monitor the
IOUT OC warning from the ADC, the followings steps must be
performed:
1.
2.
3.
If an IOUT sample is taken that is above the configured
IOUT OC value, the GPO1/ ALERT1 /CONV pin is taken
low, signaling an interrupt to a processor.
HANDLING/CLEARING AN ALERT
When faults/warnings are configured on the GPOx/ ALERTx pins,
the pins become active to signal an interrupt to the processor.
(These pins are active low, unless inversion is enabled.) The
GPOx/ ALERTx signal performs the function of an SMBAlert.
Note that the GPOx/ ALERTx pins can become active indepen-
dently of each other, but they are always made inactive together.
A processor can respond to the interrupt in one of two basic ways:
•
•
Set a threshold level with the IOUT_OC_WARN_LIMIT
command.
Set the IOUT_OC_WARN_EN1 bit in the
ALERT1_CONFIG register
Start the power monitor sampling on IOUT.
If there is only one device on the bus, the processor can
simply read the status bytes and issue a CLEAR_FAULTS
command to clear all the status bits, which causes the
deassertion of the GPOx/ ALERTx line. If there is a persistent
fault—for example, an undervoltage on the input—the status
bits remain set after the CLEAR_FAULTS command is
executed because the fault has not been removed. However,
the GPOx/ ALERTx line is not pulled low unless a new fault/
warning becomes active. If the cause of the SMBAlert is a
power monitor generated warning and the power monitor
is running continuously, the next sample generates a new
SMBAlert after the CLEAR_FAULTS command is issued.
If there are many devices on the bus, the processor can issue
an SMBus alert response address command to find out
which device asserted the SMBAlert line. The processor
can read the status bytes from that device and issue a
CLEAR_FAULTS command.
Data Sheet