adm1075-2aruz-rl7 Analog Devices, Inc., adm1075-2aruz-rl7 Datasheet - Page 11

• Manufacturer Part Number: adm1075-2aruz-rl7
• Description: −48 V Hot Swap Controller And Digital Power Monitor With Pmbus Interface
• Manufacturer: Analog Devices, Inc.

Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTION
Table 5. Pin Function Descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin No.
Mnemonic
DRAIN
VIN
UVH
UVL
OV
PLIM
VCAP
ADC_V
ISET
SS
TIMER
LATCH
ADR
SHDN
RESTART
Description
Connect to the drain pin of the FET through a resistor. The current in this resistor is used to determine
the V
Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via a shunt resistor. A 1 μF
capacitor to VEE is recommended on the VIN pin.
Undervoltage Rising Input Pin. An external resistor divider is used from the supply to this pin to allow
an internal comparator to detect if the supply is under the UVH limit.
Undervoltage Falling Input Pin. An external resistor divider is used from the supply to this pin to allow
an internal comparator to detect if the supply is under the UVL limit.
Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an
internal comparator to detect if the supply is above the OV limit.
The voltage on this pin is proportional to the V
current limit automatically adjusts to maintain constant power across the FET.
A capacitor with a value of 1 μF or greater should be placed on this pin to maintain good accuracy.
This is an internal regulated supply. This pin can be used as a reference to program the ISET pin
voltage.
This pin is used to read back the input voltage using the internal ADC. It can be connected to the OV
string or a separate divider.
This pin allows the current limit threshold to be programmed. The default limit is set when this pin is
connected directly to VCAP. Alternatively, using a resistor divider from VCAP, the current limit can be
adjusted to achieve a user defined sense voltage. An external reference can also be used.
A capacitor is used on this pin to set the inrush current soft start ramp profile. The voltage on the soft
start pin controls the current sense voltage limit, allowing control over the inrush current profile.
Timer Pin. An external capacitor, C
turns off when the voltage on the TIMER pin exceeds the upper threshold.
This pin signals the device latching off after an overcurrent fault. This pin is also used to configure the
desired retry scheme. See the Hot Swap Fault Retry section for additional details.
PMBus Address Pin. This pin can be tied low, tied to VCAP, left floating, or tied low through a resistor to
set four different PMBus addresses.
Drive this pin low to shut down the gate. Internal weak pull-up to VIN.
This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for
additional details.
Falling Edge Triggered 10 sec Automatic Restart. The gate remains off for 10 seconds, and then powers
back up. Internal weak pull-up to VIN. This pin is also used to configure the desired retry scheme. See
the Hot Swap Fault Retry section for additional details.
DS
of the MOSFET. This is used for
ADC_V
LATCH
DRAIN
TIMER
SHDN
VCAP
PLIM
ISET
ADR
UVH
UVL
VIN
OV
SS
10
11
12
13
14
1
2
3
4
5
6
7
8
9
(Not to Scale)
Figure 3. Pin Configuration
ADM1075
TOP VIEW
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24
18
17
16
15
28
27
26
25
23
22
21
20
19
TIMER
VEE_G
GATE
SENSE+
SENSE–
VEE
SPLYGD
ADC_AUX
PWRGD
SCL
SDAI
SDAO
GPO2/ALERT2
GPO1/ALERT1/CONV
RESTART
, sets an initial timing cycle delay and a fault delay. The GATE pin
PWRGD
DS
.
voltage of the FET. As the PLIM voltage changes, the
ADM1075