adm1075-2aruz-rl7 Analog Devices, Inc., adm1075-2aruz-rl7 Datasheet - Page 22

• Manufacturer Part Number: adm1075-2aruz-rl7
• Description: −48 V Hot Swap Controller And Digital Power Monitor With Pmbus Interface
• Manufacturer: Analog Devices, Inc.

ADM1075
SETTING THE CURRENT LIMIT (ISET)
The maximum current limit is partially determined by selecting
a sense resistor to match the current sense voltage limit on the
controller for the desired load current. However, as currents
become larger, the sense resistor value becomes smaller and
resolution can be difficult to achieve when selecting the appropri-
ate sense resistor value. The
sense voltage limit to deal with this issue. The device allows the
user to program the required current sense voltage limit from
15 mV to 25 mV for the
for the ADM1075-2.
The default value of 20 mV/40 mV is achieved by connecting
the ISET pin directly to the VCAP pin (VCAP > 1.65 V ISET
reference select threshold). This configures the device to use an
internal 1 V reference, which equates to 20 mV/40 mV at the
sense inputs (see Figure 47(a)).
To set the sense voltage in the 15 mV to 50 mV range, a resistor
divider is used to apply a reference voltage to the ISET pin (see
Figure 47(b)). The VCAP pin has a 2.7 V internally generated
voltage that can be used to set a voltage at the ISET pin.
C1
0 .1V
Figure 46. Interaction of Soft Start, Foldback, and ISET Current Limits
1V
V
Figure 47. (a) Fixed 20 mV/40 mV Current Sense Limit
VCAP
(b) Adjustable 15 mV to 50 mV Current Sense Limit
ISET
ISET
(A)
(PARTIAL)
ADM1075
ADM1075-1
VEE
ADM1075
CURRENT LIMIT
REFERENCE
C1
FLB
and from 30 mV to 50 mV
SS
provides an adjustable
R2
R1
VCAP
ISET
(B)
(PARTIAL)
ADM1075
t
VEE
Rev. 0 | Page 22 of 52
Assuming V
divider should be sized to set the ISET voltage as follows:
where V
be used as the pull-up supply for setting the I
VCAP pin should not be used for any other purpose. To
guarantee accuracy specifications, care must be taken to not
load the VCAP pin by more than 100 μA.
SOFT START
A capacitor connected to the SS pin determines the inrush
current profile. Before the FET is enabled, the output voltage of
the current limit reference selector block is clamped at 100 mV.
This, in turn, holds the current limit reference at approximately
2 mV for the
the FET is requested to turn on, the SS pin is held at ground
until the voltage between the SENSE+ and SENSE− pins
(V
When the load current generates a sense voltage equal to V
10 μA current source is enabled, which charges the SS capacitor
and results in a linear ramping voltage on the SS pin. The
current limit reference also ramps up accordingly, allowing the
regulated load current to ramp up, while avoiding sudden
transients during power-up. The SS capacitor value is given by
where I
For example, a 10 nF capacitor gives a soft start time of 1 ms.
Note that the SS voltage may intersect with the PLIM or
foldback (FLB) voltage, and the current limit reference may
change to follow PLIM (see Figure 46). This has minimal
impact on startup because the output voltage rises at a similar
rate to SS.
CONSTANT POWER FOLDBACK (PLIM)
Foldback is a method that actively reduces the current limit as
the voltage drop across the FET increases. It keeps the power
across the FET below the programmed value during power-up,
overcurrent, or short-circuit events. This allows a smaller FET
to be used, resulting in significant cost savings. The foldback
method employed is a constant power foldback scheme, meaning
power in the FET is held constant regardless of the V
FET. This simplifies the task of ensuring that the FET is always
operating within the SOA region.
The
monitoring the voltage on the drain of the FET (via the PLIM
pin). The device relies on the principle that the source of the
FET is at the most negative expected supply voltage, and the
magnitude of the drain voltage is relative to that of the V
the FET. Using a resistor divider from the drain of the FET to
SENSE
ADM1075
V
V
V
C
CB
ISET
ISET
) reaches the circuit breaker voltage, V
SS
SS
SENSE
= V
=
= 10 μA, and t is the SS ramp time.
= (V
= (V
I
V
SS
ISET
SENSECL
is the sense voltage limit. The VCAP rail can also
ISET
ADM1075-1
SENSE
SENSE
×
detects the voltage drop across the FET by
equals the voltage on the ISET pin, the resistor
t
− V
× 50) for ADM1075-1 or
× 25) for ADM1075-2
CBOS
or 4 mV for the ADM1075-2. When
2
CB
C address. The
Data Sheet
.
DS
of the
DS
CB
of
, a