adm1075-2aruz-rl7 Analog Devices, Inc., adm1075-2aruz-rl7 Datasheet - Page 5

• Manufacturer Part Number: adm1075-2aruz-rl7
• Description: −48 V Hot Swap Controller And Digital Power Monitor With Pmbus Interface
• Manufacturer: Analog Devices, Inc.

Data Sheet
SPECIFICATIONS
VEE = −48 V, V
Table 1.
Parameter
SYSTEM SUPPLY
SHUNT REGULATOR
UV PINS—UNDERVOLTAGE DETECTION
OV PIN—OVERVOLTAGE DETECTION
GATE PIN
SENSE+, SENSE−
VCAP
ISET
ADM1075-1
Undervoltage Falling Threshold, V
Total Undervoltage Hysteresis
Gate Voltage High
Gate Voltage Low
Pull-Up Current
Pull-Down Current (Severe OC)
Pull-Down On-Time (Severe OC)
Gate Hold-Off Resistance
Hot Swap Sense Voltage
Voltage Transient Immunity
Typical Operating Voltage
Operating Supply Voltage Range, VIN
Quiescent Supply Current
Undervoltage Lockout, V
Undervoltage Lockout Hysteresis
Power Directly Without Shunt
Undervoltage Rising Threshold, V
Undervoltage Fault Filter
UV Propagation Delay
UVL/UVH Input Current
Overvoltage Rising Threshold, V
Overvoltage Hysteresis Current
Overvoltage Fault Filter
OV Propagation Delay
OV Input Current
Pull-Down Current (Regulation)
Pull-Down Current (UV/OV/OC)
SENSE+, SENSE− Input Current, I
SENSE+, SENSE− Input Imbalance, I
Internally Regulated Voltage, V
ISET Reference Select Threshold, V
ISET Internal Reference, V
Gain of Current Sense Amplifier, AV
ISET Input Current, I
Hot Swap Sense Voltage Current Limit,
V
SENSECL
ONLY (GAIN = 50)
SENSE
= (V
ISET
SENSE+
UVLO_RISING
CLREF
− V
VCAP
OVR
SENSEx
UVH
UVL
ISETRSTH
SENSE−
ΔSENSEx
CSAMP
) = 0 mV, shunt regulation current = 10 mA, T
Min
−80
11.5
9.2
0.99
0.887
3.5
0.99
4.3
1.75
11
−50
100
5
750
8
2.66
1.35
19.4
24.5
19.5
14.5
Typ
−200
12.3
1.0
0.9
100
5
1
1.0
5
2
1
12
10
10
1500
20
2.7
1.5
1
50/25
20
25
20
15
Rev. 0 | Page 5 of 52
Max
−35
13
5.5
9.2
600
11.5
1.01
0.913
7.5
8
50
1.01
5.7
3.75
4
50
13
100
−30
2000
16
100
1
2.74
1.65
100
20.6
25.5
20.5
15.5
Unit
V
V
V
mA
V
mV
V
V
V
mV
μs
μs
nA
V
μA
μs
μs
nA
V
mV
μA
μA
mA
mA
μs
Ω
μA
μA
V
V
V
V/V
nA
mV
mV
mV
mV
Test Conditions/Comments
Shunt regulation voltage, I
Determined by external component, R
maximum I
ADM1075 section)
VIN = 13 V
When UVL and UVH are tied together
UV low to GATE pull-down active
OV high to GATE pull-down active
I
I
V
V
V
V
0 V ≤ VIN ≤ (V
V
V
I
0 ≤ I
If V
Accuracies included in total sense voltage accuracies
Accuracies included in total sense voltage accuracies
V
V
V
V
V
GATE
GATE
ΔSENSEx
J
GATE
GATE
GATE
GATE
SENSE
SENSE
ISET
ISET
ISET
ISET
ISET
= −40°C to +105°C, unless otherwise noted.
ISET
= −1.0 μA
= 100 μA
VCAP
≤ VCAP
> 1.65 V; V
= 1.25 V; V
= 1.0 V; V
= 0.75 V; V
= 0 V to 8 V; V
≥ 2 V
≥ 2 V
≥ 6 V
≤ 65 mV for ADM1075-1, per individual pin;
≤ 130 mV for ADM1075-2, per individual pin
> V
= I
≤ 100 μA; C
SENSE+
ISETRSTH
IN
dependent on T
GATE
GATE
− I
GATE
GATE
GATE
an internal 1 V reference (V
SENSE−
= 3 V; I
= 2 V)
= 3 V; I
= 3 V; I
= 3 V; I
SS
VCAP
= 2 V
= 1 μF
GATE
GATE
GATE
GATE
IN
= 0 μA; V
= 5.5 mA to 30 mA,
= 0 μA; V
= 0 μA; V
= 0 μA; V
A
, θ
JA
(see the Powering the
SS
SS
SS
SS
≥ 2 V; V
SHUNT
≥ 2 V; V
≥ 2 V; V
≥ 2 V; V
ADM1075
CLREF
PLIM
) is used
PLIM
PLIM
PLIM
= 0 V
= 0 V
= 0 V
= 0 V