adm1075-2aruz-rl7 Analog Devices, Inc., adm1075-2aruz-rl7 Datasheet - Page 50
adm1075-2aruz-rl7
Manufacturer Part Number
adm1075-2aruz-rl7
Description
−48 V Hot Swap Controller And Digital Power Monitor With Pmbus Interface
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADM1075-2ARUZ-RL7.pdf
(52 pages)
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ADM1075
READ VAUX REGISTER
Address: 0xDD, Reset: 0x0000, Name: READ_VAUX
Table 40. Bit Descriptions for READ_VAUX
Bits
[15:12]
[11:0]
VAUX OV WARN LIMIT REGISTER
Address: 0xDE, Reset: 0x0FFF, Name: VAUX_OV_WARN_LIMIT
Table 41. Bit Descriptions for VAUX_OV_WARN_LIMIT
Bits
[15:12]
[11:0]
VAUX UV WARN LIMIT REGISTER
Address: 0xDF, Reset: 0x0000, Name: VAUX_UV_WARN_LIMIT
Table 42. Bit Descriptions for VAUX_UV_WARN_LIMIT
Bits
[15:12]
[11:0]
VAUX STATUS REGISTER
Address: 0xF6, Reset: 0x00, Name: STATUS_VAUX
Table 43. Bit Descriptions for STATUS_VAUX
Bits
7
6
[5:0]
RESERVED
Bit Name
RESERVED
READ_VAUX
Bit Name
VAUX_OV_WARN_LIMIT
Bit Name
RESERVED
VAUX_UV_WARN_LIMIT
Bit Name
VAUX_OV_WARN
VAUX_UV_WARN
RESERVED
Settings
Settings
Settings
Settings
0
1
0
1
Description
Always reads as 0000.
Undervoltage threshold for the ADC_AUX pin measurement,
expressed in ADC codes.
Always reads as 0000.
Description
Always reads as 0000.
Overvoltage threshold for the ADC_AUX pin measurement,
expressed in ADC codes.
Always reads as 000000.
Description
Output voltage from the ADC_AUX pin measurement, expressed in
ADC codes.
Description
Latched register.
No overvoltage condition was detected on the ADC_AUX pin by the
power monitor using the VAUX_OV_WARN_LIMIT command.
An overvoltage condition was detected on the ADC_AUX pin by the
power monitor using the VAUX_OV_WARN_LIMIT command.
Latched register.
No undervoltage condition was detected on the ADC_AUX pin by
the power monitor using the VAUX_UV_WARN_LIMIT command.
An undervoltage condition was detected on the ADC_AUX pin by
the power monitor using the VAUX_UV_WARN_LIMIT command.
Rev. 0 | Page 50 of 52
Data Sheet
Reset
0x0
0x0
Reset
0x0
0x0
0x0
Reset
0x0
0xFFF
Reset
0x0
0x0
Access
R
R
Access
R
RW
Access
R
RW
Access
R
R
R
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