fin12a Fairchild Semiconductor, fin12a Datasheet - Page 7

• Manufacturer Part Number: fin12a
• Description: Fin12a Mserdes Low Voltage 12-bit Bi-directional Serializer/deserializer With Multiple Frequency Ranges Preliminary
• Manufacturer: Fairchild Semiconductor

Embedded Word Clock Operation
The FIN12A sends and receives serial data source syn-
chronously with a bit clock. The bit clock has been modified
to create a word boundary at the end of each data word.
The word boundary has been implemented by skipping a
low clock pulse. This appears in the serial clock stream as
3 consecutive bit times where signal CKSO remains HIGH.
In order to implement this sort of scheme two extra data
bits are required. During the word boundary phase the data
will toggle either HIGH-then-LOW or LOW-then-HIGH
dependent upon the last bit of the actual data word. Table 2
provides some examples showing the actual data word and
the data word with the word boundary bits added. Note that
a 12-bit word will be extended to 14 bits during serial trans-
mission. Bit 13 and Bit 14 are defined with-respect-to Bit
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold value
equal to ½ of V
when the device is operating as a serializer. When the
device is operating as a deserializer the inputs are gated
off to conserve power.
The LVCMOS 3-STATE output buffers are rated for a
source/sink current of 2 mAs at 1.8V. The outputs are
active when the DIRI signal is asserted LOW. When the
DIRI signal is asserted HIGH the bi-directional LVCMOS I/
Os will be in HIGH-Z state. Under purely capacitive load
conditions the output will swing between GND and V
The LVCMOS I/O buffers incorporate bushold functionality
to allow for pins to maintain state when they are not driven.
The bushold circuitry only consumes power during signal
transitions.
FFFh
555h
xxxh
xxxh
Hex
DDP
FIGURE 6. LVCMOS I/O
. The input buffers are only operational
12 Bit Data Words
0101 01010 0101b
0xxx xxxx xxxxb
1xxx xxxx xxxxb
1111 1111 1111b
Binary
TABLE 2. Word Boundary Data Bits
DDP
.
7
12. Bit 13 will always be the inversion of Bit 12 and Bit 14
will always be the same as Bit 12. This insures that a “0”
“1” and a “1”
embedded word phase where CKSO is HIGH.
The serializer generates the word boundary data bits and
the boundary clock condition and embeds them into the
serial data stream. The deserializer looks for the end of the
word boundary condition to capture and transfer the data to
the parallel port. The deserializer only uses the embedded
word boundary information to find and capture the data.
These boundary bits are then stripped prior to the word
being sent out of the parallel port.
Differential I/O Circuitry
The differential I/O circuitry is a low power variant of LVDS.
The differential outputs operate in the same fashion as
LVDS by sourcing and sinking a balanced current through
the output pair. Like LVDS an input source termination
resistor is required to develop a voltage at the differential
input pair. The FIN12A device incorporates an internal ter-
mination resistor on the CKSI receiver and a gated internal
termination resistor on the DS input receiver. The gated ter-
mination resistor insures proper termination regardless of
direction of data flow.
2FFFh
1555h
1xxxh
2xxxh
FIGURE 7. Bi-directional Differential I/O Circuitry
Hex
12 Bit Data Word with Word Boundary
“0” transition will always occur during the
01 0101 0101 0101b
10 1111 1111 1111b
01 0xxx xxxx xxxxb
10 1xxx xxxx xxxxb
Binary
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Preliminary