fin12a Fairchild Semiconductor, fin12a Datasheet - Page 3

• Manufacturer Part Number: fin12a
• Description: Fin12a Mserdes Low Voltage 12-bit Bi-directional Serializer/deserializer With Multiple Frequency Ranges Preliminary
• Manufacturer: Fairchild Semiconductor

Pin Description
Note 1: The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180 degrees with respect to the other device the serial
connections will properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross.
Control Logic Circuitry
The FIN12A has the ability to be used as a 12-bit Serializer
or a 12-bit Deserializer. Terminals S1 and S2 must be set to
accommodate the clock reference input frequency range of
the serializer. The table below shows the terminal program-
ming of these options based on the S1 and S2 control ter-
minals. The DIRI terminal controls whether the device is
the serializer or a deserializer. When DIRI is asserted
LOW, the device is configured as a deserializer. When the
DIRI terminal is asserted HIGH, the device will be config-
ured as a serializer. Changing the state on the DIRI signal
will reverse the direction of the I/O signals and generate
the opposite state signal on DIRO. For unidirectional oper-
ation the DIRI terminal should be hardwired to the HIGH or
LOW state and the DIRO terminal should be left floating.
For bi-directional operation the DIRI of the master device
will be driven by the system and the DIRO signal of the
master will be used to drive the DIRI of the slave device.
Turn-Around Functionality
The device passes and inverts the DIRI signal through the
device asynchronously to the DIRO signal. Care must be
taken by the system designer to insure that no contention
occurs between the deserializer outputs and the other
devices on this port. Optimally the peripheral device driving
CKSO , CKSO
CKSI , SKSI
DSO / DSI
DSO / DSI
Pin Name
STROBE
DP[1:12]
CKREF
DIRO
V
V
V
GND
CKP
DIRI
S1
S2
DDP
DDS
DDA
DIFF-OUT
DIFF-I/O
I/O Type
DIFF-IN
Supply
Supply
Supply
Supply
OUT
OUT
I/O
IN
IN
IN
IN
IN
Number
of Pins
12
1
1
1
2
2
2
1
1
1
1
1
1
1
0
LVCMOS Parallel I/O. Direction controlled by DIRI terminal.
LVCMOS Clock Input and PLL Reference
LVCMOS Strobe Signal for Latching Data into the Serializer
LVCMOS Word Clock Output
LpLVDS Differential Serial I/O Data Signals (Note 1)
LpLVDS Differential Deserializer Input Bit Clock
LpLVDS Differential Serializer Output Bit Clock
LVCMOS Mode Selection terminals used to define
LVCMOS Control Input
LVCMOS Control Output
Power Supply for Parallel I/O and Translation Circuitry
Power Supply for Core and Serial I/O
Power Supply for Analog PPL Circuitry
Use Bottom Ground Plane for Ground Signals
frequency range for the RefClock, CKREF
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO(I) : Positive signal of DSO(I) pair
DSO(I) : Negative signal of DSO(I) pair
CKSI: Refers to signal pair
CKSI : Positive signal of CKSI pair
CKSI : Negative signal of CKSI pair
CKSO: Refers to signal pair
CKSO : Positive signal of CKSO pair
CKSO : Negative signal of CKSO pair
Used to control direction of Data Flow:
Inversion of DIRI
DIRI
DIRI
“1” Serializer,
“0” Deserializer
3
Number
the serializer should be put into a HIGH Impedance state
prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer the dedicated outputs will remain
at the last logical value asserted. This value will only
change if the device is once again turned around into a
deserializer and the values are overwritten.
Mode
0
1
2
3
Description of Signals
S2 S1 DIRI
0
0
0
1
1
1
1
TABLE 1. Control Logic Circuitry
0
1
1
0
0
1
1
X
1
0
1
0
1
0
Power-Down Mode
12-Bit Serializer,
20MHz to 56MHz CKREF
12-Bit Deserializer
12-Bit Serializer,
5MHz to 15MHz CKREF
12-Bit Deserializer
12-Bit Serializer,
10MHz to 30MHz CKREF
12-Bit Deserializer
Description
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Preliminary