fin12a Fairchild Semiconductor, fin12a Datasheet - Page 6

• Manufacturer Part Number: fin12a
• Description: Fin12a Mserdes Low Voltage 12-bit Bi-directional Serializer/deserializer With Multiple Frequency Ranges Preliminary
• Manufacturer: Fairchild Semiconductor

www.fairchildsemi.com
Deserializer Operation Mode
The operation of the deserializer is only dependent upon
the data received on the DSI data signal pair and the CKSI
clock signal pair. The following two sections describe the
operation of the deserializer under two distinct serializer
source conditions. References to the CKREF and STROBE
signals refer to the signals associated with the serializer
device used in generating the serial data and clock signals
that are inputs to the deserializer.
When operating in this mode the internal serializer circuitry
is disabled including the parallel data input buffers. If there
is a CKREF signal provided then the CKSO serial clock will
continue to transmit bit clocks.
Deserializer Operation:
When the DIRI signal is asserted LOW the device will be
configured as a deserializer. Data will be captured on the
serial port and deserialized through use of the bit clock
sent with the data. The word boundary is defined in the
actual clock and data signal. Parallel data will be generated
at the time the word boundary is detected. The falling edge
of CKP will occur coincident with the data transition. The
rising edge of CKP will be generated approximately 7 bit
DIRI equals 0
(Serializer Source: CKREF equals STROBE)
(Serializer Source: CKREF does not equal STROBE)
(Serializer Source: CKREF equals STROBE)
FIGURE 4. Deserializer Timing Diagram
FIGURE 5. Deserializer Timing Diagram
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times later. When no embedded word boundary occurs
then no pulse on CKP will be generated and CKP will
remain HIGH.
Deserializer Operation:
The logical operation of the deserializer remains the same
regardless of if the CKREF is equal in frequency to the
STROBE or at a higher frequency than the STROBE. The
actual serial data stream presented to the deserializer will
however be different because it will have non-valid data
bits sent between words. The duty cycle of CKP will vary
based on the ratio of the frequency of the CKREF signal to
the STROBE signal. The frequency of the CKP signal will
be equal to the STROBE frequency. The falling edge of
CKP will coincident with data transition. The LOW time of
the CKP signal will be equal to ½ (7 bit times) of the
CKREF period. The CKP HIGH time will be equal to
STROBE period ½ of the CKREF period. Figure 5 is rep-
resentative of a waveform that could be seen when CKREF
is not equal to STROBE. If CKREF was significantly faster
than additional non-valid data bits would occur between
data words.
PwrDwn equals 1
DIRI equals 0
(Serializer Source: CKREF does not equal STROBE)
Preliminary